AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 96

• Manufacturer Part Number: AT89C51CC01
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC01

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 1.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

Registers
96
A/T89C51CC01
Table 58. CANGCON Register
CANGCON (S:ABh)
CAN General Control Register
Reset Value = 0000 0000b
Number
ABRQ
Bit
7
7
6
5
4
3
2
1
0
Bit Mnemonic Description
AUTOBAUD
SYNCTTC
OVRQ
ENA/STB
OVRQ
ABRQ
GRES
TEST
6
TTC
Abort Request
Not an auto-resetable bit. A reset of the ENCH bit (message object control
and DLC register) is done for each message object. The pending transmission
communications are immediately aborted but the on-going communication will
be terminated normally, setting the appropriate status flags, TXOK or RXOK.
Overload frame request (initiator)
Auto-resetable bit.
Set to send an overload frame after the next received message.
Cleared by the hardware at the beginning of transmission of the overload
frame.
Network in Timer Trigger Communication
set to select node in TTC.
clear to disable TTC features.
Synchronization of TTC
When this bit is set the TTC timer is caught on the last bit of the End Of
Frame.
When this bit is clear the TTC timer is caught on the Start Of Frame.
This bit is only used in the TTC mode.
AUTOBAUD
set to active listening mode.
Clear to disable listening mode
Test mode. The test mode is intended for factory testing and not for customer
use.
Enable/Standby CAN Controller
When this bit is set, it enables the CAN controller and its input clock.
When this bit is clear, the on-going communication is terminated normally and
the CAN controller state of the machine is frozen (the ENCH bit of each
message object does not change).
In the standby mode, the transmitter constantly provides a recessive level; the
receiver is not activated and the input clock is stopped in the CAN controller.
During the disable mode, the registers and the mailbox remain accessible.
Note that two clock periods are needed to start the CAN controller state of the
machine.
General Reset (software reset)
Auto-resetable bit. This reset command is ‘ORed’ with the hardware reset in
order to reset the controller. After a reset, the controller is disabled.
TTC
5
SYNCTTC
4
AUTOBAUD
3
TEST
2
ENA
1
4129N–CAN–03/08
GRES
0