AT89LP216 Atmel Corporation, AT89LP216 Datasheet - Page 16

• Manufacturer Part Number: AT89LP216
• Manufacturer: Atmel Corporation

Specifications of AT89LP216

• Flash (kbytes): 2 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 14
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.125
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI/OCD
• Watchdog: Yes

10.4
10.5
11. Power Saving Modes
11.1
11.2
11.2.1
16
Watchdog Reset
Software Reset
Idle Mode
Power-down Mode
AT89LP216
Interrupt Recovery from Power-down
When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles.
Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the
watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times
out. See
Watchdog.
The CPU may generate an internal 16-clock cycle reset pulse by writing the software reset
sequence 5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDT-
CON. See
The AT89LP216 supports two different power-reducing modes: Idle and Power-down. These
modes are accessed through the PCON register.
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU
state is preserved in its entirety, including the RAM, stack pointer, program counter, program
status word, and accumulator. The Port pins hold the logic states they had at the time that Idle
was activated. Idle mode leaves the peripherals running in order to allow them to wake up the
CPU when an interrupt is generated. The timers, UART, SPI, and GPI blocks continue to func-
tion during Idle. The comparator and watchdog may be selectively enabled or disabled during
Idle. Any enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode
with an interrupt, the interrupt will immediately be serviced, and following RETI the next instruc-
tion to be executed will be the one following the instruction that put the device into Idle.
Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops
the oscillator, disables the BOD and powers down the Flash memory in order to minimize power
consumption. Only the power-on circuitry will continue to draw power during Power-down. Dur-
ing Power-down, the power supply voltage may be reduced to the RAM keep-alive voltage. The
RAM contents will be retained, but the SFR contents are not guaranteed once V
reduced. Power-down may be exited by external reset, power-on reset, or certain interrupts.
Three external interrupts may be configured to terminate Power-down mode. XTAL1 or XTAL2,
when not used for the crystal oscillator or external clock, may be used to exit Power-down
through external interrupts INT0 (P3.2) and INT1 (P3.3). To wake up by external interrupt INT0
or INT1, that interrupt must be enabled and configured for level-sensitive operation. General
purpose interrupt 3 (GPI3) can also wake up the device when the RST pin is disabled. GPI3
must be enabled and configured for low level detection in order to terminate Power-down.
When terminating Power-down by an interrupt, two different wake-up modes are available.
When PWDEX in PCON is zero, the wake-up period is internally timed as shown in
At the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an
internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has timed out. After the time-out period the interrupt service routine will
begin. The time-out period is controlled by the Start-up Timer Fuses (see
15). The interrupt pin need not remain low for the entire time-out period.
“Programmable Watchdog Timer” on page 57
“Software Reset” on page 58
for more information on software reset.
for details on the operation of the
Table 10-1 on page
3621E–MICRO–11/10
CC
Figure
has been
11-1.