AT89LP216 Atmel Corporation, AT89LP216 Datasheet - Page 27

• Manufacturer Part Number: AT89LP216
• Manufacturer: Atmel Corporation

Specifications of AT89LP216

• Flash (kbytes): 2 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 14
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.125
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI/OCD
• Watchdog: Yes

14. Enhanced Timer/Counters
14.1
3621E–MICRO–11/10
Mode 0 – Variable Width Timer/Counter
Table 13-5.
The AT89LP216 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. As a Timer, the
register increase every clock cycle by default. Thus, the register counts clock cycles. Since a
clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency.
The timer rate can be prescaled by a value between 1 and 16 using the Timer Prescaler (see
Table 9-2 on page
As a Counter, the register is incremented in response to a l-to-0 transition at its corresponding
input pin, T0 or T1. The external input is sampled every clock cycle. When the samples show a
high in one cycle and a low in the next cycle, the count is incremented. The new count value
appears in the register during the cycle following the one in which the transition was detected.
Since 2 clock cycles are required to recognize a l-to-0 transition, the maximum count rate is 1/2
of the oscillator frequency. There are no restrictions on the duty cycle of the input signal, but it
should be held for at least one full clock cycle to ensure that a given level is sampled at least
once before it changes.
Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes:
variable width timer, 16-bit auto-reload timer, 8-bit auto-reload timer, and split timer. The control
bits C/T in the Special Function Register TMOD select the Timer or Counter function. The bit
pairs (M1, M0) in TMOD select the operating modes.
Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from
1 to 8 bits depending on the PSC bits in TCONB, giving the timer a range of 9 to 16 bits.
By default the timer is configured as a 13-bit timer compatible to Mode 0 in the standard 8051.
Figure 14-1
rolls over from all “1”s to all “0”s, it sets the Timer interrupt flag TF1. The counter input is enabled
to the Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. Setting GATE = 1 allows the Timer
to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is a control
bit in the Special Function Register TCON. GATE is in TMOD. The 13-bit register consists of all
8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should
be ignored. Setting the run flag (TR1) does not clear the registers.
Note:
Port Pin
P3.2
P3.3
P3.4
P3.5
P3.6
RH1/RL1 are not required by Timer 1 during Mode 0 and may be used as temporary storage
registers.
shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count
Mode 0:
Port Pin Alternate Functions (Continued)
PxM0.y
P3M0.2
P3M0.3
P3M0.4
P3M0.5
13). Both Timers share the same prescaler.
Configuration Bits
not configurable
Time-out Period
PxM1.y
P3M1.2
P3M1.3
P3M1.4
P3M1.5
=
------------------------------------------------------ -
Oscillator Frequency
Alternate
CMPOUT
Function
CLKOUT
256
INT0
INT1
T0
T1
×
2
PSC0
+
Notes
Internal RC Oscillator Only
Internal RC Oscillator or
External Clock Source Only
Pin is tied to comparator output
1
×
(
TPS
AT89LP216
+
1
)
27