AT89LP216 Atmel Corporation, AT89LP216 Datasheet - Page 70

• Manufacturer Part Number: AT89LP216
• Manufacturer: Atmel Corporation

Specifications of AT89LP216

• Flash (kbytes): 2 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 14
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.125
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI/OCD
• Watchdog: Yes

24.4
Table 24-3.
24.5
24.6
70
Symbol
LOAD
SUCCESS
WRTINH
BUSY
Bit
Status Register
DATA Polling
Flash Security
AT89LP216
Function
Load flag. Cleared low by the load page buffer command and set high by the next memory write. This flag signals that
the page buffer was previously loaded with data by the load page buffer command.
Success flag. Cleared low at the start of a programming cycle and will only be set high if the programming cycle
completes without interruption from the brownout detector.
Write Inhibit flag. Cleared low by the brownout detector (BOD) whenever programming is inhibited due to V
below the minimum required programming voltage. If a BOD episode occurs during programming, the SUCCESS flag
will remain low after the cycle is complete. WRTINH low also forces BUSY low.
Busy flag. Cleared low whenever the memory is busy programming or if write is currently inhibited.
Status
–
7
Register
The current state of the memory may be accessed by reading the status register. The status reg-
ister is shown in
The AT89LP216 implements DATA polling to indicate the end of a programming cycle. While the
device is busy, any attempted read of the last byte written will return the data byte with the MSB
complemented. Once the programming cycle has completed, the true value will be accessible.
During Erase the data is assumed to be FFH and DATA polling will return 7FH. When writing
multiple bytes in a page, the DATA value will be the last data byte loaded before programming
begins, not the written byte with the highest physical address within the page.
The AT89LP216 provides two Lock Bits for Flash Code Memory security. Lock bits can be left
unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in
Lock bits can only be erased (set to FFh) by Chip Erase. Lock bit mode 2 disables programming
of all memory spaces, including the User Signature Array and User Configuration Fuses. User
fuses must be programmed before enabling Lock bit mode 2 or 3. Lock bit mode 3 implemented
mode 2 and also blocks reads from the code memory; however, reads of the User Signature
Array, Atmel Signature Array, and User Configuration Fuses are still allowed.
Table 24-4.
Mode
Program Lock Bits (by address)
–
6
1
2
3
Lock Bit Protection Modes
Table
–
5
00h
FFh
00h
00h
24-3.
–
4
01h
FFh
FFh
00h
LOAD
Protection Mode
No program lock features
Further programming of the Flash is disabled
Further programming of the Flash is disabled and verify
(read) is also disabled; OCD is disabled
3
SUCCESS
2
WRTINH
1
3621E–MICRO–11/10
BUSY
0
CC
Table
falling
24-4.