AT89LP216 Atmel Corporation, AT89LP216 Datasheet - Page 38

• Manufacturer Part Number: AT89LP216
• Manufacturer: Atmel Corporation

Specifications of AT89LP216

• Flash (kbytes): 2 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 14
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.125
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI/OCD
• Watchdog: Yes

17. Serial Interface
17.1
38
Multiprocessor Communications
AT89LP216
The serial interface on the AT89LP216 implements a Universal Asynchronous Receiver/Trans-
mitter (UART). The UART has the following features:
The serial interface is full duplex, which means it can transmit and receive simultaneously. It is
also receive-buffered, which means it can begin receiving a second byte before a previously
received byte has been read from the receive register. (However, if the first byte still has not
been read when reception of the second byte is complete, one of the bytes will be lost.) The
serial port receive and transmit registers are both accessed at the Special Function Register
SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically
separate receive register. The serial port can operate in the following four modes.
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination
register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initi-
ated in the other modes by the incoming start bit if REN = 1.
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes,
9 data bits are received, followed by a stop bit. The 9th bit goes into RB8. Then comes a stop bit.
The port can be programmed such that when the stop bit is received, the serial port interrupt is
activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON.
The following example shows how to use the serial interrupt for multiprocessor communications.
When the master processor must transmit a block of data to one of several slaves, it first sends
out an address byte that identifies the target slave. An address byte differs from a data byte in
that the 9th bit is “1” in an address byte and “0” in a data byte. With SM2 = 1, no slave is
• Full Duplex Operation
• 8 or 9 Data Bits
• Framing Error Detection
• Multiprocessor Communication Mode with Automatic Address Recognition
• Baud Rate Generator Using Timer 1
• Interrupt on Receive Buffer Full or Transmission Complete
• Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data
• Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
• Mode 2: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
• Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
bits are transmitted/received, with the LSB first. The baud rate is fixed at 1/2 the oscillator
frequency.
8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in the Special
Function Register SCON. The baud rate is variable based on Timer 1.
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th
data bit (TB8 in SCON) can be assigned the value of “0” or “1”. For example, the parity bit
(P, in the PSW) can be moved into TB8. On receive, the 9th data bit goes into RB8 in the
Special Function Register SCON, while the stop bit is ignored. The baud rate is
programmable to either 1/16 or 1/32 the oscillator frequency.
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the
same as Mode 2 in all respects except the baud rate, which is variable based on Timer 1 in
Mode 3.
3621E–MICRO–11/10