AT89LP216 Atmel Corporation, AT89LP216 Datasheet - Page 9

• Manufacturer Part Number: AT89LP216
• Manufacturer: Atmel Corporation

Specifications of AT89LP216

• Flash (kbytes): 2 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 14
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.125
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI/OCD
• Watchdog: Yes

8. Enhanced CPU
3621E–MICRO–11/10
The AT89LP216 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard
8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance is
due to two factors. First, the CPU fetches one instruction byte from the code memory every clock
cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions in
parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz. A simple
example is shown in
The MCS-51 instruction set allows for instructions of variable length from 1 to 3 bytes. In a sin-
gle-clock-per-byte-fetch system this means each instruction takes at least as many clocks as it
has bytes to execute. The majority of instructions in the AT89LP216 follow this rule: the instruc-
tion execution time in clock cycles equals the number of bytes per instruction with a
few exceptions. Branches and Calls require an additional cycle to compute the target address
and some other complex instructions require multiple cycles. See
page 59
examples of 1- and 2-byte instructions.
Figure 8-1.
Figure 8-2.
Register Operand Fetch
ALU Operation Execute
Fetch Next Instruction
for more detailed information on individual instructions.
Total Execution Time
(n+1)
(n+2)
Result Write Back
Parallel Instruction Fetches and Executions
Single-cycle ALU Operation (Example: INC R0)
System Clock
n
System Clock
th
th
th
Instruction
Instruction
Instruction
Figure
8-1.
Fetch
T
T
n
1
Execute
Fetch
T
n+1
T
2
“Instruction Set Summary” on
Figures 8-2 and 8-3
Execute
AT89LP216
Fetch
T
n+2
T
3
show
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