ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 105

• Manufacturer Part Number: ATmega162
• Manufacturer: Atmel Corporation

Specifications of ATmega162

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 6
• Input Capture Channels: 2
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Special Function IO
Register – SFIOR
2513K–AVR–07/09
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 45. Prescaler for Timer/Counter0, Timer/Counter1, and Timer/Counter3
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR2 and PSR310 bits is kept, hence keeping the corresponding
prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted
and can be configured to the same value without the risk of one of them advancing during con-
figuration. When the TSM bit is written to zero, the PSR2 and PSR310 bits are cleared by
hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR310: Prescaler Reset Timer/Counter3, Timer/Counter1, and Timer/Counter0
When this bit is one, the Timer/Counter3, Timer/Counter1, and Timer/Counter0 prescaler will be
reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note
that Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler and a
reset of this prescaler will affect all three timers.
Bit
Read/Write
Initial Value
CS30
CS31
CS32
1. The synchronization logic on the input pins (
TSM
R/W
7
0
TIMER/COUNTER3 CLOCK SOURCE
0
PSR321
CK
XMBK
ExtClk
R/W
clk
6
0
T3
< f
clk_I/O
XMM2
R/W
5
0
T1
/2) given a 50/50% duty cycle. Since the edge detector uses
CS10
CS11
CS12
XMM1
R/W
Clear
4
0
TIMER/COUNTER1 CLOCK SOURCE
0
XMM0
R/W
10-BIT T/C PRESCALER
clk
3
0
Tn/T0)
T1
PUD
R/W
is shown in
2
0
T0
CS00
CS01
CS02
PSR2
R/W
1
0
Figure
ATmega162/V
TIMER/COUNTER1 CLOCK SOURCE
0
PSR310
R/W
0
0
44.
clk
T0
(1)
clk_I/O
SFIOR
/2.5.
105