ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 154

• Manufacturer Part Number: ATmega162
• Manufacturer: Atmel Corporation

Specifications of ATmega162

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 6
• Input Capture Channels: 2
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Timer/Counter
Interrupt Mask
Register – TIMSK
154
ATmega162/V
•
•
• Bit 4 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
• Bit 2 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt
Flag Register – TIFR.
Bit
Read/Write
Initial Value
cycles, it executes the interrupt routine, and resumes execution from the instruction
following SLEEP.
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an
incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2
must be done through a register synchronized to the internal I/O clock domain.
Synchronization takes place for every rising TOSC1 edge. When waking up from Power-
save mode, and the I/O clock (clk
value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC
clock after waking up from Power-save mode is essentially unpredictable, as it depends on
the wake-up time. The recommended procedure for reading TCNT2 is thus as follows:
1. Write any value to either of the registers OCR2 or TCCR2.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT2.
During asynchronous operation, the synchronization of the Interrupt Flags for the
Asynchronous Timer takes three processor cycles plus one timer cycle. The Timer is
therefore advanced by at least one before the processor can read the Timer value causing
the setting of the Interrupt Flag. The output compare pin is changed on the Timer clock and
is not synchronized to the processor clock.
TOIE1
R/W
7
0
OCIE1A
R/W
6
0
OCIE1B
R/W
5
0
I/O
OCIE2
) again becomes active, TCNT2 will read as the previous
R/W
4
0
TICIE1
R/W
3
0
TOIE2
R/W
2
0
TOIE0
R/W
1
0
OCIE0
R/W
0
0
TIMSK
2513K–AVR–07/09