ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 92

• Manufacturer Part Number: ATmega162
• Manufacturer: Atmel Corporation

Specifications of ATmega162

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 6
• Input Capture Channels: 2
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Force Output
Compare
Compare Match
Blocking by TCNT0
Write
92
ATmega162/V
Figure 35. Output Compare Unit, Block Diagram
The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Reg-
ister to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0 Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR0 Buffer Register, and if double buffering is disabled
the CPU will access the OCR0 directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0) bit. Forcing Compare Match will not set the
OCF0 Flag or reload/clear the Timer, but the OC0 pin will be updated as if a real Compare
Match had occurred (the COM01:0 bits settings define whether the OC0 pin is set, cleared or
toggled).
All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0 to be initialized
to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is
enabled.
bottom
FOCn
top
OCRn
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMn1:0
TCNTn
OCFn (Int.Req.)
OCn
2513K–AVR–07/09