ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 20

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ATmega162

Manufacturer Part Number
ATmega162
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega162

Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
35
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
6
Input Capture Channels
2
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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EEPROM Read/Write
Access
The EEPROM Address
Register – EEARH and
EEARL
20
ATmega162/V
“Memory Programming” on page 231
in SPI, JTAG, or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time
to run at a voltage lower than specified as minimum for the clock frequency used. See
ing EEPROM Corruption” on page 24
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
• Bits 15..9 – Res: Reserved Bits
These bits are reserved bits in the ATmega162 and will always read as zero.
• Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
Bit
Read/Write
Initial Value
EEAR7
R/W
15
R
X
7
0
EEAR6
R/W
14
R
X
6
0
EEAR5
R/W
13
R
X
5
0
contains a detailed description on EEPROM Programming
for details on how to avoid problems in these situations.
EEAR4
R/W
12
R
X
4
0
EEAR3
R/W
11
3
R
0
X
Table
EEAR2
R/W
10
R
2
0
X
1. A selftiming function, however, lets
EEAR1
R/W
R
9
1
0
X
EEAR8
EEAR0
R/W
R/W
8
0
X
X
EEARH
EEARL
2513K–AVR–07/09
“Prevent-
CC

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