ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 91

• Manufacturer Part Number: ATmega162
• Manufacturer: Atmel Corporation

Specifications of ATmega162

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 6
• Input Capture Channels: 2
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Counter Unit
Output Compare
Unit
2513K–AVR–07/09
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
34
Figure 34. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the clock select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the output Compare Output
OC0. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
The Timer/Counter Overflow (TOV0) Flag is set according to the mode of operation selected by
the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the
Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1 and Global
Interrupt Flag in SREG is set), the Output Compare Flag generates an output compare interrupt.
The OCF0 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0
Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform gen-
erator uses the match signal to generate an output according to operating mode set by the
WGM01:0 bits and Compare Output mode (COM01:0) bits. The max and bottom signals are
used by the waveform generator for handling the special cases of the extreme values in some
modes of operation
Figure 35
count
direction
clear
clk
top
bottom
shows a block diagram of the counter and its surroundings.
Tn
shows a block diagram of the output compare unit.
DATA BUS
T
0 is present or not. A CPU write overrides (has priority over) all counter clear or
TCNTn
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
(See “Modes of Operation” on page
T
0). clk
94.
direction
T
count
clear
0 can be generated from an external or internal clock source,
bottom
Control Logic
top
TOVn
(Int.Req.)
clk
T0
Tn
in the following.
94.).
Clock Select
( From Prescaler )
Detector
Edge
ATmega162/V
Tn
Figure
91