ATmega16A Atmel Corporation, ATmega16A Datasheet - Page 94

• Manufacturer Part Number: ATmega16A
• Manufacturer: Atmel Corporation

Specifications of ATmega16A

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

94
ATmega16A
Figure 16-2. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con-
taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower 8
bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT1H I/O location, the CPU accesses the High byte temporary register
(TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read,
and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows
the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data
bus. It is important to notice that there are special cases of writing to the TCNT1 Register when
the counter is counting that will give unpredictable results. The special cases are described in
the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the
timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
whether clk
count operations.
The counting sequence is determined by the setting of the Waveform Generation Mode bits
(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OC1x. For more details about advanced counting
sequences and waveform generation, see
The Timer/Counter Overflow (TOV1) Flag is set according to the mode of operation selected by
the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
Count
Direction
Clear
clk
TOP
BOTTOM
T
TCNTnH (8-bit)
1
TEMP (8-bit)
T
1
is present or not. A CPU write overrides (has priority over) all counter clear or
TCNTn (16-bit Counter)
DATA BUS
T
1
TCNTnL (8-bit)
). The clk
(8-bit)
Increment or decrement TCNT1 by 1.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Timer/Counter clock.
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
T
1
can be generated from an external or internal clock source,
Direction
Count
Clear
“Modes of Operation” on page
Control Logic
TOP
BOTTOM
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
99.
8154B–AVR–07/09
Tn