ATtiny87 Atmel Corporation, ATtiny87 Datasheet - Page 107
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ATtiny87
Manufacturer Part Number
ATtiny87
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny87
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Price
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11. Timer/Counter1 Prescaler
11.1
11.1.1
11.1.2
11.1.3
8265B–AVR–09/10
Overview
Internal Clock Source
Prescaler Reset
External Clock Source
Most bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
used as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the
state of the prescaler will have implications for situations where a prescaled clock is used. One
example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler
(6 > CSn[2:0] > 1). The number of system clock cycles from when the timer is enabled to the
first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler
divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it
is connected to.
An external clock source applied to the T1 pin can be used as Timer/Counter clock (clk
The T1 pin is sampled once every system clock cycle by the pin synchronization logic. The
synchronized (sampled) signal is then passed through the edge detector.
functional equivalent block diagram of the T1 synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (
transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn[2:0] = 6) edge it detects.
Figure 11-1. T1 Pin Sampling
CLK_I/O
/256, or f
Tn
clk
I/O
CLK_I/O
D
LE
Q
/1024.
Synchronization
CLK_I/O
D
Q
). Alternatively, one of four taps from the prescaler can be
T1
pulse for each positive (CSn[2:0] = 7) or negative
D
Q
Edge Detector
CLK_I/O
Figure 11-1
clk
Select Logic)
(To Clock
I/O
Tn_sync
/8, f
). The latch is
CLK_I/O
shows a
T
/64,
107
1).