ATtiny87 Atmel Corporation, ATtiny87 Datasheet - Page 213
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ATtiny87
Manufacturer Part Number
ATtiny87
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny87
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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18.2
18.2.1
18.2.2
8265B–AVR–09/10
Register Description
ADCSRB – ADC Control and Status Register B
ACSR – Analog Comparator Control and Status Register
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the positive input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the positive input of the Analog Comparator.
When the Analog to Digital Converter (ADC) is configured as single ended input channel, it is
possible to select any of the ADC[10:0] pins to replace the positive input to the Analog Com-
parator. The ADC multiplexer (MUX[4:0]) is used to select this input, and consequently, the
ADC must be switched off to utilize this feature.
• Bits 5:4 – ACIR[1:0]: Analog Comparator Internal Voltage Reference Select
When ACIRS bit is set in ADCSRA register, these bits select a voltage reference for the nega-
tive input to the Analog Comparator, see
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption
in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must
be disabled by clearing the ACIE bit of ACSR register. Otherwise an interrupt can occur when
the bit is changed.
• Bit 6 – ACIRS: Analog Comparator Internal Reference Select
When this bit is set an Internal Reference Voltage replaces the negative input to the Analog
Comparator (c.f.
If ACIRS is cleared, AIN0 is applied to the negative input to the Analog Comparator.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO.
The synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is
set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
Bit
(0x7B)
Read/Write
Initial Value
Bit
0x30 (0x50)
Read/Write
Initial Value
ACD
R/W
R/W
BIN
7
0
Table 18-2 on page
7
0
ACIRS
ACME
R/W
R/W
6
0
6
0
ACIR1
ACO
N/A
R/W
R
5
5
0
212).
Table 18-2 on page
ACIR0
R/W
R/W
ACI
4
0
4
0
ACIE
R/W
R
3
–
0
3
0
ADTS2
ACIC
R/W
R/W
2
0
212.
2
0
ADTS1
ACIS1
R/W
R/W
1
0
1
0
ADTS0
ACIS0
R/W
R/W
0
0
0
0
ADCSRB
ACSR
213