ATtiny87 Atmel Corporation, ATtiny87 Datasheet - Page 119
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ATtiny87
Manufacturer Part Number
ATtiny87
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny87
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.7
8265B–AVR–09/10
Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1A/B). If TCNT equals OCR1A/B the comparator signals a match. A match will set the
Output Compare Flag (OCF1A/B) at the next timer clock cycle. If enabled (OCIE1A/B = 1), the
Output Compare Flag generates an Output Compare interrupt. The OCF1A/B flag is automati-
cally cleared when the interrupt is executed. Alternatively the OCF1A/B flag can be cleared by
software by writing a logical one to its I/O bit locations. The Waveform Generator uses the
match signal to generate an output according to operating mode set by the Waveform Gener-
ation mode (WGM1[3:0]) bits and Compare Output mode (COM1A/B[1:0]) bits. The TOP and
BOTTOM signals are used by the Waveform Generator for handling the special cases of the
extreme values in some modes of operation
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value
(i.e., counter resolution). In addition to the counter resolution, the TOP value defines the
period time for waveforms generated by the Waveform Generator.
Figure 12-4
gram that are not directly a part of the Output Compare unit are gray shaded.
Figure 12-4. Output Compare Unit, Block Diagram
The OCR1A/B Register is double buffered when using any of the twelve Pulse Width Modula-
tion (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR1A/B Compare Register to either TOP or BOTTOM of the counting sequence. The syn-
chronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
shows a block diagram of the Output Compare unit. The elements of the block dia-
OCRnxH Buf.(8-bit)
OCRnxH (8-bit)
BOTTOM
OCRnx Buffer (16-bit Register)
TEMP (8-bit)
TOP
OCRnx (16-bit Register)
OCRnxL Buf.(8-bit)
OCRnxL (8-bit)
DATA BUS
(See “Modes of Operation” on page
Waveform Generator
WGMn3:0
=
(16-bit Comparator )
(8-bit)
COMnx1:0
TCNTnH (8-bit)
OCFnx
TCNTn (16-bit Counter)
(Int.Req.)
TCNTnL (8-bit)
122.)
OCnxW
OCnxX
OCnxU
OCnxV
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