ATtiny87 Atmel Corporation, ATtiny87 Datasheet - Page 136
ATtiny87
Manufacturer Part Number
ATtiny87
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny87
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.11.3
12.11.4
136
ATtiny87/ATtiny167
TCCR1C – Timer/Counter1 Control Register C
TCCR1D – Timer/Counter1 Control Register D
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to zero
when TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1nx output is changed according to its COM1A/B[1:0] and OC1nx bits setting. Note
that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in
the COM1A/B[1:0] bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bits 7:4 – OC1Bi: Output Compare Pin Enable for Channel B
The OC1Bi bits enable the Output Compare pins of Channel B as shown in
page
• Bits 3:0 – OC1Ai: Output Compare Pin Enable for Channel A
The OC1Ai bits enable the Output Compare pins of Channel A as shown in
page
Bit
(0x82)
Read/Write
Initial Value
Bit
(0x83)
Read/Write
Initial Value
122.
122.
FOC1A
OC1BX
R/W
R/W
7
0
7
0
OC1BW
FOC1B
R/W
R/W
6
0
6
0
OC1BV
R/W
R
5
–
0
5
0
OC1BU
R/W
R
4
–
0
4
0
OC1AX
R/W
R
3
–
0
3
0
OC1AW
R/W
R
2
–
0
2
0
OC1AV
R/W
1
–
R
0
1
0
OC1AU
R/W
Figure 12-6 on
Figure 12-6 on
0
–
R
0
0
0
8265B–AVR–09/10
TCCR1C
TCCR1D
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