ATtiny87 Atmel Corporation, ATtiny87 Datasheet - Page 23
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ATtiny87
Manufacturer Part Number
ATtiny87
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny87
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATtiny87-A15MZ
Manufacturer:
Atmel
Quantity:
12 127
Company:
Part Number:
ATtiny87-A15SZ
Manufacturer:
Atmel
Quantity:
3 722
Company:
Part Number:
ATtiny87-A15XZ
Manufacturer:
Atmel
Quantity:
8 895
Part Number:
ATtiny87-SU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
ATtiny87-SUR
Manufacturer:
Atmel
Quantity:
323
Company:
Part Number:
ATtiny87-XUR
Manufacturer:
ATMEL
Quantity:
8 272
3.5.4
3.5.5
3.5.6
8265B–AVR–09/10
GPIOR2 – General Purpose I/O Register 2
GPIOR1 – General Purpose I/O Register 1
GPIOR0 – General Purpose I/O Register 0
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the
selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been
written to one by software, hardware clears the bit to zero after four clock cycles.
• Bit 1 – EEPE: EEPROM Program Enable
The EEPROM Program Enable Signal EEPE is the programming enable signal to the
EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn
bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, oth-
erwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit
is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the
next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the
correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger
the EEPROM read. The EEPROM read access takes one instruction, and the requested data
is available immediately. When the EEPROM is read, the CPU is halted for four cycles before
the next instruction is executed. The user should poll the EEPE bit before starting the read
operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to
change the EEAR Register.
Bit
0x2B (0x4B)
Read/Write
Initial Value
Bit
0x2A (0x4A)
Read/Write
Initial Value
Bit
0x1E (0x3E)
Read/Write
Initial Value
GPIOR27
GPIOR17
GPIOR07
R/W
R/W
R/W
7
0
7
0
7
0
GPIOR16
GPIOR06
GPIOR26
R/W
R/W
R/W
0
0
6
0
6
6
GPIOR25
GPIOR15
GPIOR05
R/W
R/W
R/W
0
5
0
5
0
5
GPIOR04
GPIOR24
GPIOR14
R/W
R/W
R/W
4
0
4
0
4
0
GPIOR13
GPIOR03
GPIOR23
R/W
R/W
R/W
3
0
3
0
3
0
GPIOR22
GPIOR12
GPIOR02
R/W
R/W
R/W
2
0
2
0
2
0
GPIOR01
GPIOR21
GPIOR11
R/W
R/W
R/W
1
0
1
0
1
0
GPIOR10
GPIOR00
GPIOR20
R/W
R/W
R/W
0
0
0
0
0
0
GPIOR1
GPIOR0
GPIOR2
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