ATtiny87 Atmel Corporation, ATtiny87 Datasheet - Page 130
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ATtiny87
Manufacturer Part Number
ATtiny87
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny87
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.10 Timer/Counter Timing Diagrams
130
ATtiny87/ATtiny167
In phase and frequency correct PWM mode, the compare units allow generation of PWM
waveforms on the OC1A/B pins. Setting the COM1A/B[1:0] bits to two will produce a
non-inverted PWM and an inverted PWM output can be generated by setting the
COM1A/B[1:0] to three (See
on the port pin if the data direction for the port pin is set as output (DDR_OC1A/B) and
OC1A/Bi is set. The PWM waveform is generated by setting (or clearing) the OC1A/B Register
at the compare match between OCR1A/B and TCNT1 when the counter increments, and
clearing (or setting) the OC1A/B Register at compare match between OCR1A/B and TCNT1
when the counter decrements. The PWM frequency for the output when using phase and fre-
quency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represents special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1A/B is set equal to BOT-
TOM the output will be continuously low and if set equal to TOP the output will be set to high
for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR1A/B Register is updated with the OCR1A/B buffer value
(only for modes utilizing double buffering).
of OCF1A/B.
Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1A/B, no Prescaling
Figure 12-12
TCNTn
OCRnx
OCFnx
(clk
clk
clk
I/O
shows the same timing data, but with the prescaler enabled.
I/O
Tn
/1)
OCRnx - 1
Table on page
f
OCnxPFCPWM
OCRnx
Figure 12-11
133). The actual OC1A/B value will only be visible
OCRnx Value
=
--------------------------- -
2 N TOP
⋅
f
clk_I/O
⋅
OCRnx + 1
shows a timing diagram for the setting
T
1) is therefore shown as a
OCRnx + 2
8265B–AVR–09/10