ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 216
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ATxmega128A1
Manufacturer Part Number
ATxmega128A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Part Number
Manufacturer
Quantity
Price
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101
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19.6.1.1
19.6.1.2
19.6.1.3
19.6.1.4
19.6.2
19.6.3
19.7
8077H–AVR–12/09
Enabling External Driver Interface
Receiving Data Packets
Transmitting Data Packets
Case 1: Address packet accepted - Direction bit set
Case 2: Address packet accepted - Direction bit cleared
Case 3: Collision
Case 4: STOP condition received.
The R/W Direction flag reflects the direction bit received with the address. This can be read by
software to determine the type of operation currently in progress.
Depending on the R/W direction bit and bus condition one of four distinct cases (1 to 4) arises
following the address packet. The different cases must be handled in software.
If the R/W Direction flag is set, this indicates a master read operation. The SCL line is forced
low, stretching the bus clock. If ACK is sent by the slave, the slave hardware will set the Data
Interrupt Flag indicating data is needed for transmit. If NACK is sent by the slave, the slave will
wait for a new condition and address match.
If the R/W Direction flag is cleared this indicates a master write operation. The SCL line is forced
low, stretching the bus clock. If ACK is sent by the slave, the slave will wait for data to be
received. Data, Repeated START or STOP can be received after this. If NACK is indicated the
slave will wait for a new START condition and address match.
If the slave is not able to send a high level or NACK, the Collision flag is set and it will disable the
data and acknowledge output from the slave logic. The clock hold is released. A START or
repeated START condition will be accepted.
Operation is the same as case 1 or 2 above with one exception. When the STOP condition is
received, the Slave Address/Stop flag will be set indicating that a STOP condition and not an
address match occurred.
The slave will know when an address packet with R/W direction bit cleared has been success-
fully received. After acknowledging this, the slave must be ready to receive data. When a data
packet is received the Data Interrupt Flag is set, and the slave must indicate ACK or NACK.
After indicating a NACK, the slave must expect a STOP or Repeated START condition.
The slave will know when an address packet, with R/W direction bit set, has been successfully
received. It can then start sending data by writing to the Slave Data register. When a data packet
transmission is completed, the Data Interrupt Flag is set. If the master indicates NACK, the slave
must stop transmitting data, and expect a STOP or Repeated START condition.
An external drivers interface can be enabled. When this is done the internal TWI drivers with
input filtering and slew rate control are bypassed. The normal I/O pin function is used and the
direction must be configured by the user software. When this mode is enabled an external TWI
compliant tri-state driver is needed for connecting to a TWI bus.
By default port pin 0 (Pn0) and 1 (Pn1) is used for SDA and SCL. The external driver interface
uses port pin 0 to 3 for the signals SDA_IN, SCL_IN, SDA_OUT and SCL_OUT.
XMEGA A
216
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