ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 253
ATxmega128A1
Manufacturer Part Number
ATxmega128A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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8077H–AVR–12/09
• Bits 5:4 - PMODE[1:0]: Parity Mode
These bits enable and set the type of parity generation according to
When enabled, the Transmitter will automatically generate and send the parity of the transmitted
data bits within each frame. The Receiver will generate a parity value for the incoming data and
compare it to the PMODE setting and if a mismatch is detected, the PERR flag in STATUS will
be set.
These bits are unused in Master SPI mode of operation.
Table 21-7.
• Bit 3 - SBMODE: Stop Bit Mode
This bit selects the number of stop bits to be inserted by the Transmitter according to
on page
This bit is unused in Master SPI mode of operation.
Table 21-8.
• Bit 2:0 - CHSIZE[2:0]: Character Size
The CHSIZE[2:0] bits sets the number of data bits in a frame according to
253. The Receiver and Transmitter use the same setting.
Table 21-9.
PMODE[1:0]
CHSIZE[2:0]
2. See
253. The Receiver ignores this setting.
000
001
010
011
100
101
110
111
00
01
10
11
PMODE Bits Settings
SBMODE Bit Settings
CHSIZE Bits Settings
”USART” on page 235
SBMODE
0
1
Group Configuration
Group Configuration
DISABLED
EVEN
ODD
5BIT
6BIT
7BIT
8BIT
9BIT
for full description of the Master SPI Mode (MSPIM) operation.
Parity mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
Character size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
Stop Bit(s)
1-bit
2-bit
Table 21-7 on page
Table 21-9 on page
XMEGA A
Table 21-8
253.
253
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