ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 242
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ATxmega128A1
Manufacturer Part Number
ATxmega128A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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21.6.2
21.7
21.7.1
21.7.2
21.7.3
8077H–AVR–12/09
Data Reception - The USART Receiver
Disabling the Transmitter
Receiving Frames
Receiver Error Flags
Parity Checker
transmission) or immediately after the last stop bit of the previous frame is transmitted. When the
Shift Register is loaded with data, it will transfer one complete frame.
The Transmit Complete Interrupt Flag (TXCIF) is set and the optional interrupt is generated
when the entire frame in the Shift Register has been shifted out and there are no new data pres-
ent in the transmit buffer.
The Transmit Data Register (DATA) can only be written when the Data Register Empty Flag
(DREIF) is set, indicating that the register is empty and ready for new data.
When using frames with less than eight bits, the most significant bits written to the DATA are
ignored. If 9-bit characters are used the ninth bit must be written to the TXB8 bit before the low
byte of the character is written to DATA.
A disabling of the Transmitter will not become effective until ongoing and pending transmissions
are completed, i.e. when the Transmit Shift Register and Transmit Buffer Register do not contain
data to be transmitted. When Transmitter is disabled it will no longer override the TxDn pin and
the pin direction is set as input.
When the Receiver is enabled, the RxD pin is given the function as the Receiver's serial input.
The direction of the pin must be set as input, which is the default pin setting.
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start
bit will be sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until
the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When
the first stop bit is received and a complete serial frame is present in the Receive Shift Register,
the contents of the Shift Register will be moved into the receive buffer. The Receive Complete
Interrupt Flag (RXCIF) is set, and the optional interrupt is generated.
The receiver buffer can be read by reading the Data Register (DATA) location. DATA should not
be read unless the Receive Complete Interrupt Flag is set. When using frames with less than
eight bits, the unused most significant bits are read as zero. If 9-bit characters are used, the
ninth bit must be read from the RXB8 bit before the low byte of the character is read from DATA.
The USART Receiver has three error flags. The Frame Error (FERR), Buffer Overflow
(BUFOVF) and Parity Error (PERR) flags are accessible from the Status Register. The error
flags are located in the receive FIFO buffer together with their corresponding frame. Due to the
buffering of the error flags, the Status Register must be read before the receive buffer (DATA),
since reading the DATA location changes the FIFO buffer.
When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and
compares the result with the parity bit of the corresponding frame. If a parity error is detected the
Parity Error flag is set.
XMEGA A
242
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