ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 430

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

34.3
34.4
34.5
8077H–AVR–12/09
8077F – 02/09
8077E – 01/09
8077D – 12/08
1.
2.
3.
4.
5.
6.
7.
1.
2.
3.
4.
1.
2.
3.
4.
5.
6
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Updated
Updated
Updated
Added ADC section
Updated
Updated
Updated data sheet cross-references.
Updated
Updated
Added ADC section
Added DAC section
Updated the front page.
Updated Feature list in
Updated
20.
Added Signtaure Row register description in Memory section, updated signature row summary
with byte addresses.
Updated
Updated lication of BODACT fuse bits in FUSEBYTE5 in
Fuses and Lockbits” on page
Updated
Updated
Updated Overview in
Updated
Updated
Inserted a new section
Updated title of the
Updated
Updated
Updated
”STATUS: Battery Backup Status Register” on page
Table 9-2 on page
”Conversion Result” on page
”Overview” on page
”Capture Channel” on page
Figure 9-5
”Capture Channel” on page
”Production Signature Row” on page 20
”MCUCR – MCU Control Register” on page
”Interrupt Vector Summary - NVM Controller” on page
”Priority Between Channels” on page
”Manually Generating Events” on page 67
”Quadrature Decoder (QDEC)” on page
Figure 13-1 ”General I/O pin functionality.” on page
Table 13-7 ”Event Channel 0 output configurations” on page
Figure 13-10 ”Port override signals and related logic” on page
Table 13-7 on page
External reset characteristics in
”DAC Output model” on page
”Interrupt vector Summary” on page
”ADC Input Model” on page
”Event System” on page
”Memories” on page
”Battery Backup System” on page
106.
149.
46.
156.
156.
294.
145: Event Channel 0 Output Configurations.
18.
65.
51.
300.
69.
and inserted
318.
and
Section 9.4.3 ”External reset” on page
44.
”Event Routing Network” on page
316.
Section 4.22 ”Register Summary -
111.
130.
115.
”User Signature Row” on page
48.
145.
137.
XMEGA A
107.
67.
430