ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 357

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.6
29.6.1
29.6.2
8077H–AVR–12/09
Register Description - PDI Instruction and Addressing Registers
Instruction Register
Pointer Register
Figure 29-14. PDI instruction set summary
These registers are all internal registers that are involved in instruction decoding or PDIBUS
addressing. None of these registers are accessible as register in a register space.
When an instruction is successfully shifted into the physical layer shift-register, it is copied into
the Instruction Register. The instruction is retained until another instruction is loaded. The rea-
son for this is that the REPEAT command may force the same instruction to be run repeatedly
requiring command decoding to be performed several times on the same instruction.
The Pointer Register is used to store an address value specifying locations within the PDIBUS
address space. During direct data access, the Pointer Register is updated by the specified num-
ber of address bytes given as operand bytes to the instruction. During indirect data access,
addressing is based on an address already stored in the Pointer Register prior to the access
REPEAT
LDCS
STCS
LDS
STS
KEY
LD
ST
0
0
0
1
1
1
1
0
Cmd
Cmd
0
1
0
1
0
1
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
Size A
Ptr
CS Address
0
0
0
Size A/B
Size B
Size B
0
Cmd
0
0
0
0
1
1
1
1
Size A - Address size (direct access)
0
0
1
1 1
Ptr - Pointer access (indirect access)
0
0
1
1 1
Size B - Data size
0
0
1
1 1
CS Address (CS - Control/Status reg.)
0
0
0
0
1
0
0
1
1 1
0 0
0
1
1 1
0
1
0
0
1
0
0
1
0
0 0
0 0
0 1
0 1
1 1
0
1
0
1
0
Byte
Word (2 Bytes)
3 Bytes
Long (4 Bytes)
*(ptr)
*(ptr++)
ptr
ptr++ - Reserved
Byte
Word (2 Bytes)
3 Bytes
Long (4 Bytes)
LDS
LD
STS
ST
LDCS (LDS Control/Status)
REPEAT
STCS (STS Control/Status)
KEY
0
1
0
1
1
Register 0
Register 1
Register 2
Reserved
Reserved
......
XMEGA A
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