ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 151

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ATxmega64A3

Manufacturer Part Number
ATxmega64A3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega64A3

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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14.2.1
14.3
8077H–AVR–12/09
Block Diagram
Definitions
The following definitions are used extensively throughout the Timer/Counter documentation:
Table 14-1.
In general the term Timer is used when the Timer/Counter clock control is handled by an internal
source and the term Counter is used if the clock is given externally (from an event).
Figure 14-2 on page 152
extensions.
Name
BOTTOM
MAX
TOP
UPDATE
Timer/Counter definitions
Description
The Counter reaches the BOTTOM when it becomes zero.
The Counter reaches MAXimum when it becomes all ones.
The Counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be equal to the period (PER) or the Compare
Channel A (CCA) register setting. This is selected by the Waveform Generator Mode.
The Timer/Counter signalizes an update when it reaches BOTTOM or TOP
dependent of the Waveform Generator Mode.
shows a detailed block diagram of the Timer/Counter without the
XMEGA A
151

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