ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 199

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.3.2
18.3.3
SYNCCTRL - Synchronisation Control/Status Register
INTCTRL - Interrupt Control Register
• Bit 0 - ENABLE: RTC Enable
Setting this bit enables the RTC. The synchronization time between the RTC and the System
Clock domains is one half RTC clock cycle from writing the register and until this has effect in
RTC clock domain, i.e until the RTC starts.
For the RTC to start running the PER Register must also be set to a different value that zero.
• Bits 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4- SYNCCNT: Enable Synchronization of the CNT register
Setting this bit will start synchronization of CNT register from the RTC clock to the System Clock
domain. The bit is automatically cleared when synchronization is done.
• Bits 3:1 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 - SYNCBUSY: RTC Synchronization Busy Flag
This flag is set when the CTRL or CNT registers are busy synchronizing from the System Clock
to the RTC clock domain. The CTRL register synchronization is triggered when it is written. The
CNT register are synchronized when the most significant byte of the register is written.
• Bits 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 3:2 - COMPINTLVL[1:0]: RTC Compare Match Interrupt Enable
These bits enable the RTC Compare Match Interrupt and select the interrupt level as described
in
enabled interrupt will trigger when the COMPIF in the INTFLAGS register is set.
Bit
+0x01
Read/Write
Reset Value
Bit
+0x02
Read/Write
Reset Value
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
7
-
R
0
7
-
R
0
6
-
R
0
6
-
R
0
5
-
R
0
5
-
R
0
SYNCCNT
R/W
4
0
4
-
R
0
COMPINTLVL[1:0]
R/W
3
3
-
R
0
0
R/W
2
2
-
R
0
0
R/W
1
1
-
R
0
0
OCINTLVL[1:0]
SYNCBUSY
R/W
R/W
0
0
0
0
SYNCCTRL
INTCTRL
123. The