ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 260

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23. Crypto Engines
23.1
23.2
23.3
8077H–AVR–12/09
Features
Overview
DES Instruction
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The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two com-
monly used standards for encryption. These are supported through an AES peripheral module
and a DES core instruction.
DES is supported by a DES instruction in the AVR XMEGA core. The 8-byte key and 8-byte data
blocks must be loaded into the Register file, and then DES must be executed 16 times to
encrypt/decrypt the data block.
The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key.
The key and data must be loaded into the module before encryption/decryption is started. It
takes 375 peripheral clock cycles before encrypted/decrypted data can be read out.
The DES instruction is a single cycle instruction, that needs to be executed 16 times subse-
quently in order to decrypt or encrypt a 64-bit (8 bytes) data block.
The data and key blocks must be loaded into the Register File before encryption/decryption is
started. The 64-bit data block (plaintext or ciphertext) is placed in registers R0-R7, where LSB of
data is placed in LSB of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (includ-
ing parity bits) is placed in registers R8-R15, with LSB of key in LSB of R8 and MSB of key in
MSB of R15.
Data Encryption Standard (DES) core instruction
Advanced Encryption Standard (AES) crypto module
DES Instruction
AES Crypto Module
– Encryption and Decryption
– DES supported
– Single-cycle DES instruction
– Encryption/Decryption in 16 clock cycles per 8-byte block
– Encryption and Decryption
– Support 128-bit keys
– Support XOR data load mode to the State memory
– Encryption/Decryption in 375 clock cycles per 16-byte block
XMEGA A
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