ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 440

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8077H–AVR–12/09
20 SPI – Serial Peripheral Interface ......................................................... 229
21 USART ................................................................................................... 235
22 IRCOM - IR Communication Module .................................................. 256
19.10
19.11
19.12
19.13
19.14
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
20.9
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.10
21.11
21.12
21.13
21.14
21.15
21.16
21.17
22.1
Register Description - TWI Slave ..................................................................223
Register Summary - TWI ...............................................................................228
Register Summary - TWI Master ...................................................................228
Register Summary - TWI Slave .....................................................................228
Interrupt Vector Summary .............................................................................228
Features ........................................................................................................229
Overview ........................................................................................................229
Master Mode ..................................................................................................230
Slave Mode ....................................................................................................230
Data Modes ...................................................................................................231
DMA Support .................................................................................................232
Register Description ......................................................................................232
Register Summary .........................................................................................234
SPI Interrupt vectors ......................................................................................234
Features ........................................................................................................235
Overview ........................................................................................................235
Clock Generation ...........................................................................................237
Frame Formats ..............................................................................................240
USART Initialization .......................................................................................241
Data Transmission - The USART Transmitter ...............................................241
Data Reception - The USART Receiver ........................................................242
Asynchronous Data Reception ......................................................................243
The Impact of Fractional Baud Rate Generation ...........................................246
USART in Master SPI Mode ..........................................................................247
USART SPI vs. SPI .......................................................................................247
Multi-processor Communication Mode ..........................................................248
IRCOM Mode of Operation ............................................................................249
DMA Support .................................................................................................249
Register Description ......................................................................................249
Register Summary .........................................................................................255
Interrupt Vector Summary .............................................................................255
Features ........................................................................................................256
XMEGA A
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