ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 60

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.14.5
8077H–AVR–12/09
TRFCNTH - DMA Channel Block Transfer Count Register H
Table 5-10.
Notes:
Table 5-11.
Note:
Table 5-12.
The Group Configuration is the “base_offset”, for example TCC1_CCA for the Timer/Counter C1
CC Channel A the transfer trigger.
The TRFCNTH and TRFCNTL register pair represents the 16-bit value TRFCNT. TRFCNT
defines the number of bytes in a block transfer. The value of TRFCNT is decremented after each
byte read by the DMA channel. When TRFCNT reaches zero, the register is reloaded with the
last value written to it.
Reading and writing 16-bit values requires special attention, for details refer to
”Accessing 16-bits Registers” on page
Bit
+0x05
Read/Write
Initial Value
TRGSRC offset value
TRGSRC offset value
TRGSRC offset value
1. For DAC only Channel 0 and 1 exists and can be used as triggers
2. Channel 4 equals ADC Channel 0 to 3 OR'ed together.
1. CC Channel C and D triggers are only available for Timer/Counter 0.
+0x00
+0x01
+0x02
+0x03
+0x04
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
0x00
0x01
R/W
DMA Trigger sources, offset values for DAC and ADC triggers
DMA Trigger sources, offset values for Timer/ Counter triggers
DMA Trigger sources, offset values for USART triggers
7
0
R/W
6
0
Group Configuration
Group Configuration
Group Configuration
R/W
5
0
CCC
CH2
CH4
ERR
CCA
CCB
CCD
RXC
DRE
CH0
CH1
CH3
OVF
(1)
(2)
(1)
12.
R/W
4
0
TRFCNT[15:8]
Description
ADC/DAC Channel 0
ADC/DAC Channel 1
ADC Channel 2
ADC Channel 3
ADC Channel 0, 1, 2, 3
Description
Overflow/Underflow
Error
Compare or Capture Channel A
Compare or Capture Channel B
Compare or Capture Channel C
Compare or Capture Channel D
Description
Receive complete
Data Register Empty
R/W
3
0
R/W
2
0
R/W
1
0
XMEGA A
R/W
0
0
Section 3.11
TRFCNTH
60