SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 180
SAM3S16C
Manufacturer Part Number
SAM3S16C
Description
Manufacturer
Atmel Corporation
Datasheet
1.SAM3S16C.pdf
(1130 pages)
Specifications of SAM3S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
Max. Operating Frequency
100 MHz
Cpu
Cortex-M3
# Of Touch Channels
39
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.20.9
138
SAM3S16
System Handler Priority Registers
The SHPR1-SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have
configurable priority.
SHPR1-SHPR3 are byte accessible. See the register summary in
their attributes.
The system fault handlers and the priority field and register for each handler are:
Table 12-32. System fault handler priority fields
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:4] of each field, and
bits[3:0] read as zero and ignore writes.
Handler
Memory management
fault
Bus fault
Usage fault
SVCall
PendSV
SysTick
Field
PRI_4
PRI_5
PRI_6
PRI_11
PRI_14
PRI_15
“System Handler Priority Register 1” on page 139
“System Handler Priority Register 2” on page 140
“System Handler Priority Register 3” on page 140
Register description
Table 12-30 on page 126
11117B–ATARM–18-Oct-11
for
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