SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 501
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SAM3S16C
Manufacturer Part Number
SAM3S16C
Description
Manufacturer
Atmel Corporation
Datasheet
1.SAM3S16C.pdf
(1130 pages)
Specifications of SAM3S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
Max. Operating Frequency
100 MHz
Cpu
Cortex-M3
# Of Touch Channels
39
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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30.5.13.2
Figure 30-9. PIO controller connection with CMOS digital image sensor
459
459
SAM3S16
SAM3S16
PDC
Functional Description
understanding and to ease reading, the following description uses an example with a CMOS dig-
ital image sensor.
The CMOS digital image sensor provides a sensor clock, an 8-bit data synchronous with the
sensor clock, and two data enables which are synchronous with the sensor clock too.
As soon as the parallel capture mode is enabled by writing the PCEN bit at 1 in PIO_PCMR
(“PIO Parallel Capture Mode Register”
CLK), the sensor data (PIODC[7:0]) and the sensor data enable signals (PIODCEN1 and
PIODCEN2) are configured automatically as INPUTS. To know which I/O lines are associated
with the sensor clock, the sensor data and the sensor data enable signals, refer to the I/O multi-
plexing table(s) in the product datasheet.
Once it is enabled, the parallel capture mode samples the data at rising edge of the sensor clock
and resynchronizes it with the PIO clock domain.
The size of the data which can be read in PIO_PCRHR
ing Register”
larger than 8 bits, then the parallel capture mode samples several sensor data to form a concat-
enated data of size defined by DSIZE. Then this data is stored in PIO_PCRHR and the flag
DRDY is set to 1 in PIO_PCISR
The parallel capture mode can be associated with a reception channel of the Peripheral DMA
Controller (PDC). This enables performing reception transfer from parallel capture mode to a
memory buffer without any intervention from the CPU. Transfer status signals from PDC are
available in PIO_PCISR through the flags ENDRX and RXBUFF (see
Interrupt Status Register” on page
The parallel capture mode can take into account the sensor data enable signals or not. If the bit
ALWYS is set to 0 in PIO_PCMR, the parallel capture mode samples the sensor data at the ris-
ing edge of the sensor clock only if both data enable signals are active (at 1). If the bit ALWYS is
set to 1, the parallel capture mode samples the sensor data at the rising edge of the sensor
clock whichever the data enable signals are.
The parallel capture mode can sample the sensor data only one time out of two. This is particu-
larly useful when the user wants only to sample the luminance Y of a CMOS digital image sensor
Data
Status
) can be programmed thanks to the DSIZE field in PIO_PCMR. If this data size is
PIO Controller
Parallel Capture
Mode
(“PIO Parallel Capture Interrupt Status Register”
PIODC[7:0]
PIODCEN2
PIODCCLK
PIODCEN1
501).
), the I/O lines connected to the sensor clock (PIODC-
(“PIO Parallel Capture Reception Hold-
PCLK
DATA[7:0]
VSYNC
HSYNC
Image Sensor
CMOS Digital
“PIO Parallel Capture
11117B–ATARM–18-Oct-11
11117B–ATARM–18-Oct-11
).
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