SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 367

• Manufacturer Part Number: SAM3S16C
• Manufacturer: Atmel Corporation

Specifications of SAM3S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 100 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 39
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 25-1.
25.6
25.6.1
Figure 25-2.
25.6.1.1
11117B–ATARM–18-Oct-11
11117B–ATARM–18-Oct-11
Connection to External Devices
Data Bus Width
SMC
NAND Flash Support
Memory Connections for Four External Devices
Memory Connection for an 8-bit Data Bus
NCS[0] - NCS[3]
A[23:0]
D[7:0]
NWE
NRD
The data bus width is 8 bits.
Figure 25-2
The SMC integrates circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller. It depends on the programming
of the SMC_NFCSx field in the CCFG_SMCNFCS Register on the Bus Matrix User Interface.
For details on this register, refer to the Bus Matrix User Interface section. Access to an external
NAND Flash device via the address space reserved to the chip select programmed.
The user can connect up to 4 NAND Flash devices with separated chip select.
The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCSx programmed is active. NANDOE and NANDWE are dis-
abled as soon as the transfer address fails to lie in the NCSx programmed address space.
SMC
shows how to connect a 512K x 8-bit memory on NCS2.
A[18:0]
NCS[2]
D[7:0]
NWE
NRD
24
8
NCS0
NCS1
NCS2
Memory Enable
Output Enable
Write Enable
A[23:0]
D[7:0]
NCS3
Write Enable
Output Enable
Memory Enable
D[7:0]
A[18:0]
Memory Enable
Memory Enable
Memory Enable
SAM3S16
SAM3S16
325
325