SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 83

• Manufacturer Part Number: SAM3S16C
• Manufacturer: Atmel Corporation

Specifications of SAM3S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 100 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 39
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.10 About the instruction descriptions
12.10.1
12.10.2
11117B–ATARM–18-Oct-11
Operands
Restrictions when using PC or SP
The CMSIS also provides a number of functions for accessing the special registers using MRS
and MSR instructions:
Table 12-15. CMSIS intrinsic functions to access the special registers
The following sections give more information about using the instructions:
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination register.
When there is a destination register in the instruction, it is usually specified before the operands.
Operands in some instructions are flexible in that they can either be a register or a constant. See
“Flexible second operand”
Many instructions have restrictions on whether you can use the Program Counter (PC) or Stack
Pointer (SP) for the operands or destination register. See instruction descriptions for more
information.
Special register
PRIMASK
FAULTMASK
BASEPRI
CONTROL
MSP
PSP
•
•
•
•
•
•
•
•
“Operands” on page 41
“Restrictions when using PC or SP” on page 41
“Flexible second operand” on page 42
“Shift Operations” on page 43
“Address alignment” on page 45
“PC-relative expressions” on page 46
“Conditional execution” on page 46
“Instruction width selection” on page
Access
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
.
CMSIS function
uint32_t __get_PRIMASK (void)
void __set_PRIMASK (uint32_t value)
uint32_t __get_FAULTMASK (void)
void __set_FAULTMASK (uint32_t value)
uint32_t __get_BASEPRI (void)
void __set_BASEPRI (uint32_t value)
uint32_t __get_CONTROL (void)
void __set_CONTROL (uint32_t value)
uint32_t __get_MSP (void)
void __set_MSP (uint32_t TopOfMainStack)
uint32_t __get_PSP (void)
void __set_PSP (uint32_t TopOfProcStack)
48.
SAM3S16
41