SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 1006

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

44.5
Table 44-9.
Note:
1006
1006
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C-0xE0
0xE4
0xE8
0xEC-0xF8
0xFC
Image Sensor Interface (ISI) User Interface
Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program
the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller.
SAM9G25
SAM9G25
Register Mapping
Register
ISI Configuration 1 Register
ISI Configuration 2 Register
ISI Preview Size Register
ISI Preview Decimation Factor Register
ISI CSC YCrCb To RGB Set 0 Register
ISI CSC YCrCb To RGB Set 1 Register
ISI CSC RGB To YCrCb Set 0 Register
ISI CSC RGB To YCrCb Set 1 Register
ISI CSC RGB To YCrCb Set 2 Register
ISI Control Register
ISI Status Register
ISI Interrupt Enable Register
ISI Interrupt Disable Register
ISI Interrupt Mask Register
DMA Channel Enable Register
DMA Channel Disable Register
DMA Channel Status Register
DMA Preview Base Address Register
DMA Preview Control Register
DMA Preview Descriptor Address Register
DMA Codec Base Address Register
DMA Codec Control Register
DMA Codec Descriptor Address Register
Reserved
Write Protection Control Register
Write Protection Status Register
Reserved
Reserved
DMA_P_ADDR
DMA_P_DSCR
DMA_C_ADDR
DMA_C_DSCR
ISI_Y2R_SET0
ISI_Y2R_SET1
ISI_R2Y_SET0
ISI_R2Y_SET1
ISI_R2Y_SET2
DMA_P_CTRL
DMA_C_CTRL
DMA_CHDR
DMA_CHER
DMA_CHSR
ISI_PDECF
ISI_WPCR
ISI_PSIZE
ISI_WPSR
ISI_CFG1
ISI_CFG2
ISI_IMR
ISI_IDR
ISI_IER
ISI_CR
ISI_SR
Name
–
–
–
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Access
–
–
–
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
0x00000000
0x00000000
0x00000000
0x00000010
0x00007102
0x01324145
0x01245e38
0x01384a4b
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset Value
0x6832cc95
–
–
–