SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 492

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.4.5
31.4.5.1
492
492
Single-buffer Transfer (Row 1)
SAM9G25
SAM9G25
Programming a Channel
Programming Examples
Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and
DMAC_CFGx, need to be programmed to set up whether single or multi-buffer transfers take
place, and which type of multi-buffer transfer is used. The different transfer types are shown in
Table 31-3 on page
The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx,
DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when
multi-buffer DMAC transfers are enabled.
1. Read the Channel Handler Status Register DMAC_CHSR.ENABLE Field to choose a
2. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
3. Program the following channel registers:
free (disabled) channel.
ing the interrupt status register, DMAC_EBCISR.
a. Write the starting source address in the DMAC_SADDRx register for channel x.
b. Write the starting destination address in the DMAC_DADDRx register for
c. Write the next descriptor address in the DMA_DSCRx register for channel x with
d. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1
e. Write the control information for the DMAC transfer in the DMAC_CTRLAx and
– i. Set up the transfer type (memory or non-memory peripheral for source and
– ii. Set up the transfer characteristics, such as:
f.
– i. Designate the handshaking interface type (hardware or software) for the source
destination) and flow control device by programming the FC of the DMAC_CTRLBx
register.
and destination peripherals. This is not required for memory. This step requires
programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests. Writing a
‘0’ activates the software handshaking interface to handle source/destination
requests.
– Transfer width for the source in the SRC_WIDTH field.
– Transfer width for the destination in the DST_WIDTH field.
– Source AHB Master interface layer in the SIF field where source resides.
– Destination AHB Master Interface layer in the DIF field where destination resides.
– Incrementing/decrementing or fixed address for source in SRC_INC field.
– Incrementing/decrementing or fixed address for destination in DST_INC field.
channel x.
0x0.
as shown in
both AUTO fields set to 0.
DMAC_CTRLBx registers for channel x. For example, in the register, you can pro-
gram the following:
Write the channel configuration information into the DMAC_CFGx register for chan-
nel x.
490.
Table 31-3 on page
490. Program the DMAC_CTRLBx register with
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11