SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 536

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.7.21
Name:
Address:
Access:
Reset:
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x444D4143 (“DMAC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x444D4143 (“DMAC” in ASCII).
Protects the registers:
WPKEY: Write Protect KEY
Should be written at value 0x50494F (“DMAC” in ASCII). Writing any other value in this field aborts the write operation of
the WPEN bit. Always reads as 0.
536
536
•
•
•
•
•
•
•
•
•
•
“DMAC Global Configuration Register” on page 514
“DMAC Enable Register” on page 515
“DMAC Channel x [x = 0..7] Source Address Register” on page 525
“DMAC Channel x [x = 0..7] Destination Address Register” on page 526
“DMAC Channel x [x = 0..7] Descriptor Address Register” on page 527
“DMAC Channel x [x = 0..7] Control A Register” on page 528
“DMAC Channel x [x = 0..7] Control B Register” on page 530
“DMAC Channel x [x = 0..7] Configuration Register” on page 532
“DMAC Channel x [x = 0..7] Source Picture in Picture Configuration Register” on page 534
“DMAC Channel x [x = 0..7] Destination Picture in Picture Configuration Register” on page 535
31
23
15
—
7
SAM9G25
SAM9G25
DMAC Write Protect Mode Register
DMAC_WPMR
0xFFFFEDE4 (0), 0xFFFFEFE4 (1)
Read-write
See
Table 31-4
30
22
14
—
6
29
21
13
—
5
28
20
12
—
4
WPKEY
WPKEY
WPKEY
27
19
11
—
3
26
18
10
—
2
25
17
—
9
1
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
WPEN
24
16
8
0