SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 1140

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30 DDR SDR SDRAM Controller (DDRSDRC) ......................................... 431
31 DMA Controller (DMAC) ....................................................................... 479
32 USB High Speed Port (UHPHS) ........................................................... 539
vi
29.3 I/O Lines Description .........................................................................................386
29.4 Multiplexed Signals ............................................................................................386
29.5 Application Example ..........................................................................................387
29.6 Product Dependencies ......................................................................................387
29.7 External Memory Mapping .................................................................................388
29.8 Connection to External Devices ........................................................................388
29.9 Standard Read and Write Protocols ..................................................................393
29.10 Automatic Wait States .....................................................................................401
29.11 Data Float Wait States .....................................................................................405
29.12 External Wait ...................................................................................................409
29.13 Slow Clock Mode .............................................................................................415
29.14 Asynchronous Page Mode ..............................................................................418
29.15 Programmable IO Delays ................................................................................421
29.16 Static Memory Controller (SMC) User Interface ..............................................422
30.1 Description .........................................................................................................431
30.2 Embedded Characteristics ................................................................................431
30.3 DDRSDRC Module Diagram .............................................................................433
30.4 Initialization Sequence .......................................................................................434
30.5 Functional Description .......................................................................................439
30.6 Software Interface/SDRAM Organization, Address Mapping ............................457
30.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface ...............................461
31.1 Description .........................................................................................................479
31.2 Embedded Characteristics ................................................................................479
31.3 Block Diagram ...................................................................................................483
31.4 Functional Description .......................................................................................484
31.5 DMAC Software Requirements .........................................................................511
31.6 Write Protection Registers .................................................................................512
31.7 DMA Controller (DMAC) User Interface ............................................................513
32.1 Description .........................................................................................................539
32.2 Embedded Characteristics ................................................................................539
32.3 Block Diagram ...................................................................................................540
32.4 Product Dependencies ......................................................................................541
SAM9G25
11032A–ATARM–27-Jul-11