SAM9G46 Atmel Corporation, SAM9G46 Datasheet - Page 1067

• Manufacturer Part Number: SAM9G46
• Manufacturer: Atmel Corporation

Specifications of SAM9G46

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45.6.2
45.6.2.1
45.6.2.2
45.6.2.3
45.6.2.4
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
DMA Software Operations
DMA Channel Descriptor (DSCR) Alignment and Structure
Programming a DMA Channel
Disabling a DMA channel
DMA Dynamic Linking of a New Transfer Descriptor
The DMA Channel Descriptor (DSCR) must be word aligned.
The DMA Channel Descriptor structure contains three fields:
Table 45-4.
DSCR + 0x4
DSCR + 0x8
• DSCR.CHXADDR: Frame Buffer base address register
• DSCR.CHXCTRL: Transfer Control register
• DSCR.CHXNEXT: Next Descriptor Address register
1. Check the status of the channel reading the CHXCHSR register.
2. Write the channel descriptor (DSCR) structure in the system memory by writing
3. If more than one descriptor is expected, the DFETCH field of DSCR.CHXCTRL is set to
4. Write the DSCR.CHXNEXT register with the address location of the descriptor struc-
5. Enable the relevant channel by writing one to the CHEN field of the CHXCHER register.
6. An interrupt may be raised if unmasked when the descriptor has been loaded.
1. Clear the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure will disable
2. Set the DSCR.CHXNEXT field of the DSCR structure will disable the channel at the
3. Writing one to the CHDIS field of the CHXCHDR register will disable the channel at the
4. Writing one to the CHRST field of the CHXCHDR register will disable the channel
5. Poll CHSR field in the CHXCHSR register until the channel is successfully disabled.
1. Write the new descriptor structure in the system memory.
2. Write the address of the new structure in the CHXHEAD register.
3. Add the new structure to the queue of descriptors by writing one to the A2QEN field of
4. The new descriptor will be added to the queue on the next frame.
5. An interrupt will be raised if unmasked, when the head descriptor structure has been
System Memory
DSCR.CHXADDR Frame base address, DSCR.CHXCTRL channel control and
DSCR.CHXNEXT next descriptor location.
one to enable the descriptor fetch operation.
ture and set DFETCH field of the DSCR.CHXCTRL register to one.
the channel at the end of the frame.
end of the frame.
end of the frame.
immediately. This may occur in the middle of the image.
the CHXCHER register.
loaded by the DMA channel.
DSCR + 0x0
DMA Channel Descriptor Structure
CTRL
NEXT
Structure Field for channel CHX
ADDR
SAM9G35
SAM9G35
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