SAM9G46 Atmel Corporation, SAM9G46 Datasheet - Page 576

• Manufacturer Part Number: SAM9G46
• Manufacturer: Atmel Corporation

Specifications of SAM9G46

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

33.7.7
Name:
Address:
Access:
• SPEED_CFG: Speed Configuration
Speed Configuration:
• TST_J: Test J Mode
0 = no effect.
1 = set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the D+ line.
• TST_K: Test K Mode
0 = no effect.
1 = set to send the K state on the UDPHS line. This enables the testing of the high output drive level on the D- line.
• TST_PKT: Test Packet Mode
0 = no effect.
1 = set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye pat-
terns, jitter, and any other dynamic waveform specifications.
• OPMODE2: OpMode2
0 = no effect.
1 = set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffing and the NRZI encoding.
576
576
Value
0
1
2
3
31
23
15
–
–
–
7
–
SAM9G35
SAM9G35
UDPHS Test Register
Name
NORMAL
HIGH_SPEED
FULL_SPEED
UDPHS_TST
0xF803C0E0
Read-write
30
22
14
–
–
–
6
–
Description2
Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host
supports it and then to automatically switch to High Speed mode
Reserved
Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug
or test purpose.
Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this
configuration, the macro will not respond to a High Speed reset handshake.
OPMODE2
29
21
13
–
–
–
5
TST_PKT
28
20
12
–
–
–
4
TST_K
27
19
11
–
–
–
3
TST_J
26
18
10
–
–
–
2
25
17
–
–
9
–
1
SPEED_CFG
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
24
16
–
–
8
–
0