SAM9G46 Atmel Corporation, SAM9G46 Datasheet - Page 182

• Manufacturer Part Number: SAM9G46
• Manufacturer: Atmel Corporation

Specifications of SAM9G46

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

21.7
21.7.1
21.8
182
Divider and PLLA Block
UTMI Phase Lock Loop Programming
SAM9G35
Divider and Phase Lock Loop Programming
16 periods of Slow Clock, so that the frequency of the 12 MHz Fast RC Oscillator or 3 to 20 MHz
Crystal Oscillator can be determined.
The PLLA embeds an input divider to increase the accuracy of the resulting clock signals. How-
ever, the user must respect the PLLA minimum input frequency when programming the divider.
Figure 21-6
Figure 21-6. Divider and PLLA Block Diagram
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLLA allows multiplication of the divider’s outputs. The PLLA clock signal has a frequency
that depends on the respective source signal frequency and on the parameters DIVA and
MULA. The factor applied to the source signal frequency is (MULA + 1)/DIVA. When MULA is
written to 0, the PLLA is disabled and its power consumption is saved. Re-enabling the PLLA
can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLLA is re-enabled or one of its parameters is changed, the LOCKA bit in
PMC_SR is automatically cleared. The values written in the PLLACOUNT field in CKGR_PLLAR
are loaded in the PLLA counter. The PLLA counter then decrements at the speed of the Slow
Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt
to the processor. The user has to load the number of Slow Clock cycles required to cover the
PLLA transient time into the PLLACOUNT field.
The PLLA clock can be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR register.
The source clock of the UTMI PLL is the Main Clock MAINCK. When the 12 MHz Fast RC Oscil-
lator is selected as the source of MAINCK, the 12 MHz frequency must also be selected
because the UTMI PLL multiplier contains a built-in multiplier of x 40 to obtain the USB High
Speed 480 MHz.
A 12 MHz crystal is needed to use the USB.
shows the block diagram of the divider and PLLA block.
MAINCK
SLCK
Divider
DIVA
PLLACOUNT
Counter
PLLA
MULA
PLLA
OUTA
LOCKA
PLLACK
11053B–ATARM–22-Sep-11