SAM9G46 Atmel Corporation, SAM9G46 Datasheet - Page 452
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
SAM9G46
Manufacturer Part Number
SAM9G46
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G46.pdf
(58 pages)
Specifications of SAM9G46
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Table 30-3.
Table 30-4.
Table 30-5.
Table 30-6.
Table 30-7.
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452
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27
27
27
27
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26
26
26
26
26
Bk[1:0]
Bk[1:0]
SAM9G35
SAM9G35
25
25
25
25
25
Bk[1:0]
Bk[1:0]
24
24
24
24
24
Linear Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns
Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns
Interleaved Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns
Interleaved Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns
Interleaved Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns
Bk[1:0]
23
23
23
23
23
22
22
22
22
22
Row[12:0]
Row[11:0]
21
21
21
21
21
Row[10:0]
Row[12:0]
Row[11:0]
20
20
20
20
20
Row[12:0]
Row[10:0]
Row[12:0]
Row[13:0]
Row[11:0]
19
19
19
19
19
Row[12:0]
Row[10:0]
Row[12:0]
Row[13:0]
Row[11:0]
18
18
18
18
18
Row[12:0]
Row[10:0]
Row[13:0]
17
17
17
17
17
Row[12:0]
16
16
16
16
16
15
15
15
15
15
CPU Address Line
CPU Address Line
CPU Address Line
CPU Address Line
CPU Address Line
14
14
14
14
14
Bk[1:0]
Bk[1:0]
Bk[1:0]
13
13
13
13
13
Bk[1:0]
Bk[1:0]
Bk[1:0]
12
12
12
12
12
Bk[1:0]
Bk[1:0]
Bk[1:0]
11
11
11
11
11
Bk[1:0]
Bk[1:0]
Bk[1:0]
10
10
10
10
10
9
9
9
9
9
8
8
8
8
8
Column[11:0]
Column[11:0]
Column[11:0]
Column[11:0]
7
Column[10:0]
7
Column[10:0]
7
Column[10:0]
7
Column[10:0]
7
Column[10:0]
Column[9:0]
Column[9:0]
Column[9:0]
Column[9:0]
Column[9:0]
6
6
6
6
6
Column[8:0]
Column[8:0]
Column[8:0]
Column[8:0]
Column[8:0]
5
5
5
5
5
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
0
0
0
0
0
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