SAM3S8C Atmel Corporation, SAM3S8C Datasheet - Page 684

• Manufacturer Part Number: SAM3S8C
• Manufacturer: Atmel Corporation

Figure 31-6. Receiver Overrun
31.5.2.5
Figure 31-7. Parity Error
31.5.2.6
Figure 31-8. Receiver Framing Error
684
684
RXRDY
OVRE
URXD
RXRDY
URXD
PARE
FRAME
RXRDY
SAM3S8/SD8
SAM3S8/SD8
URXD
S
Parity Error
Receiver Framing Error
D0
S
S
D1
D0
D0
D2
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in UART_MR. It then compares the result with the received parity
bit. If different, the parity error bit PARE in UART_SR is set at the same time the RXRDY is set.
The parity bit is cleared when the control register UART_CR is written with the bit RSTSTA
(Reset Status) at 1. If a new character is received before the reset status command is written,
the PARE bit remains at 1.
When a start bit is detected, it generates a character reception when all the data bits have been
sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error)
bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until
the control register UART_CR is written with the bit RSTSTA at 1.
D1
D1
D3
D2
D2
D4
D3
D3
D5
D4
D4
D6
D5
D5
D7
D6
D6
P
Wrong Parity Bit
D7
D7
stop
P
P
S
Detected at 0
stop
Stop Bit
stop
D0
D1
D2
D3
RSTSTA
RSTSTA
D4
D5
D6
D7
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
P
stop
RSTSTA