SAM3S8C Atmel Corporation, SAM3S8C Datasheet - Page 949

• Manufacturer Part Number: SAM3S8C
• Manufacturer: Atmel Corporation

35.7.40
Name:
Address:
Access:
This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in
page
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the
waveform period.
Only the first 16 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
939.
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
31
23
15
–
7
(
------------------------------------------------------- -
(
------------------------------------------------------------------ -
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
(
---------------------------------------------
(
-------------------------------------------------------- -
2
2
X
CRPDUPD
×
×
×
PWM Channel Period Update Register
X
CPRDUPD
CPRDUPD
MCK
×
PWM_CPRDUPDx [x=0..3]
0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3]
Write-only
MCK
MCK
CPRDUPD
MCK
×
DIVA
30
22
14
–
6
)
×
DIVA
)
)
or
)
or
(
-------------------------------------------------------- -
CRPDUPD
(
------------------------------------------------------------------ -
2
×
29
21
13
–
5
CPRDUPD
MCK
×
MCK
DIVB
×
)
DIVB
28
20
12
–
4
CPRDUPD
CPRDUPD
CPRDUPD
)
27
19
11
–
3
“PWM Write Protect Status Register” on
26
18
10
–
2
SAM3S8/SD8
SAM3S8/SD8
25
17
–
9
1
24
16
–
8
0
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