SAM3S8C Atmel Corporation, SAM3S8C Datasheet - Page 915
SAM3S8C
Manufacturer Part Number
SAM3S8C
Description
Manufacturer
Atmel Corporation
- Current page: 915 of 1143
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35.7.8
Name:
Address:
Access:
• CHIDx: Counter Event on Channel x
0 = No new counter event has occurred since the last read of the PWM_ISR1 register.
1 = At least one counter event has occurred since the last read of the PWM_ISR1 register.
• FCHIDx: Fault Protection Trigger on Channel x
0 = No new trigger of the fault protection since the last read of the PWM_ISR1 register.
1 = At least one trigger of the fault protection since the last read of the PWM_ISR1 register.
Note:
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
31
23
15
–
–
–
7
–
Reading PWM_ISR1 automatically clears CHIDx and FCHIDx flags.
PWM Interrupt Status Register 1
PWM_ISR1
0x4002001C
Read-only
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
FCHID3
CHID3
27
19
11
–
–
3
FCHID2
CHID2
26
18
10
–
–
2
FCHID1
CHID1
SAM3S8/SD8
SAM3S8/SD8
25
17
–
9
–
1
FCHID0
CHID0
24
16
–
8
–
0
915
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