AD5757 Analog Devices, AD5757 Datasheet - Page 11

• Manufacturer Part Number: AD5757
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5757

• Resolution (bits): 16bit
• Dac Update Rate: 60kSPS
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: SPI

Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3, 4
5
6
7
8
9
10
11
12, 17
13
14
Mnemonic
R
R
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DV
DGND
LDAC
CLEAR
SET_B
SET_A
DD
Description
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I
temperature drift performance. See the Device Features section.
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I
temperature drift performance. See the Device Features section.
Ground Reference Point for Internal Reference.
Address Decode for the Device Under Test (DUT) on the Board.
Address Decode for the DUT on the Board.
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at
clock speeds of up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 5.
Digital Supply. The voltage range is from 2.7 V to 5.5 V.
Digital Ground.
Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When
tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held
high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at
the falling edge of LDAC (see
LDAC pin must not be left unconnected.
Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed
clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more
information. When CLEAR is active, the DAC output register cannot be written to.
INDICATOR
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD SHOULD BE CONNECTED TO AGND, OR ALTERNATIVELY,
IT CAN BE LEFT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT
THE PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
REFGND
REFGND
CLEAR
R
R
ALERT
FAULT
DGND
SYNC
SCLK
LDAC
SET_B
SET_A
DV
PIN 1
SDIN
SDO
AD0
AD1
DD
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Figure 3
Figure 7. Pin Configuration
Rev. B | Page 11 of 44
(Not to Scale)
AD5757
TOP VIEW
). Using this mode, all analog outputs can be updated simultaneously. The
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMP
I
V
AV
SW
GNDSW
GNDSW
SW
AGND
SW
GNDSW
GNDSW
SW
AGND
V
I
OUT_C
OUT_B
BOOST_C
BOOST_B
CC
C
D
A
B
DCDC_C
C
D
A
B
AD5757
OUT_B
OUT_A