AD5757 Analog Devices, AD5757 Datasheet - Page 28

• Manufacturer Part Number: AD5757
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5757

• Resolution (bits): 16bit
• Dac Update Rate: 60kSPS
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: SPI

AD5757
Gain Register
The 16-bit gain register, as shown in Table 10, allows the user to
adjust the gain of each channel in steps of 1 LSB. This is done by
setting the DREG[2:0] bits to 010. It is possible to write the
same gain code to all four DAC channels at the same time by
setting the DREG[2:0] bits to 011. The gain register coding is
straight binary as shown in Table 11. The default code in the
gain register is 0xFFFF. In theory, the gain can be tuned across
the full range of the output. In practice, the maximum recom-
mended gain trim is about 50% of programmed range to maintain
accuracy. See the Digital Offset and Gain Control section for
more information.
Table 10. Programming the Gain Register
R/W
0
Table 11. Gain Register
Gain Adjustment
+65,535 LSBs
+65,534 LSBs
…
1 LSB
0 LSBs
Table 12. Programming the Offset Register
R/W
0
Table 13. Offset Register Options
Offset Adjustment
+32,767 LSBs
+32,766 LSBs
…
No Adjustment (Default)
…
−32,767 LSBs
−32,768 LSBs
Table 14. Programming the Clear Code Register
R/W
0
DUT_AD1
DUT_AD1
DUT_AD1
Device address
Device address
Device address
DUT_AD0
DUT_AD0
DUT_AD0
OF15
1
1
…
1
…
0
0
G15
…
0
0
DREG2
0
1
1
DREG2
1
OF14
1
1
…
0
…
0
0
DREG2
1
DREG1
1
G14
1
1
…
0
0
DREG1
0
OF13
1
1
…
0
…
0
0
DREG1
1
Rev. B | Page 28 of 44
DREG0
0
G13
1
1
…
0
0
DREG0
0
OF12 to OF4
1
1
…
0
…
0
0
DREG0
0
Offset Register
The 16-bit offset register, as shown in Table 12, allows the user to
adjust the offset of each channel by −32,768 LSBs to +32,767 LSBs
in steps of 1 LSB. This is done by setting the DREG[2:0] bits to
100. It is possible to write the same offset code to all four DAC
channels at the same time by setting the DREG[2:0] bits to 101.
The offset register coding is straight binary as shown in Table 13.
The default code in the offset register is 0x8000, which results in
zero offset programmed to the output. See the Digital Offset
and Gain Control section for more information.
Clear Code Register
The 16-bit clear code register allows the user to set the clear
value of each channel as shown in Table 14. It is possible, via
software, to enable or disable on a per channel basis which
channels are cleared when the CLEAR pin is activated. The
default clear code is 0x0000. See the Asynchronous Clear
section for more information.
DAC_AD1
G12 to G4
1
1
…
0
0
DAC_AD1
OF3
1
1
…
0
…
0
0
DAC_AD1
DAC channel address
DAC channel address
DAC channel address
DAC_AD0
G3
1
1
…
0
0
DAC_AD0
OF2
1
1
…
0
…
0
0
DAC_AD0
OF1
1
0
…
0
…
0
0
D15 to D0
Gain adjustment
G2
1
1
…
0
0
D15 to D0
Offset adjustment
Data Sheet
G1
1
0
…
0
0
D15 to D0
Clear code
OF0
G0
1
0
…
1
0
1
0
…
0
…
0
0