AD5757 Analog Devices, AD5757 Datasheet - Page 29

• Manufacturer Part Number: AD5757
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5757

• Resolution (bits): 16bit
• Dac Update Rate: 60kSPS
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: SPI

Data Sheet
CONTROL REGISTERS
When writing to a control register, the format shown in Table 15
must be used. See Table 8 for information on the configuration
of Bit D23 to Bit D16. The control registers are addressed by setting
the DREG[2:0] bits to 111 and then setting the CREG[2:0] bits
to the appropriate decode address for that register, according to
Table 16. These CREG bits select among the various control
registers.
Table 15. Writing to a Control Register
MSB
D23
R/W
Table 16. Register Access Decode
CREG2 (D15)
0
0
0
0
1
Table 17. Programming the Main Control Register
D15
0
1
Table 18. Main Control Register Functions
Bit
STATREAD
EWD
WD1, WD0
OUTEN_ALL
DCDC_ALL
MSB
X = don’t care.
D14
0
D22
DUT_AD1
D13
1
Enable status readback during a write. See the Device Features section.
Enable watchdog timer. See the Device Features section for more information.
Enables the output on all four DACs simultaneously.
When set, powers up the dc-to-dc converter on all four channels simultaneously.
Description
STATREAD = 1, enable.
STATREAD = 0, disable (default).
EWD = 1, enable watchdog.
EWD = 0, disable watchdog (default).
Timeout select bits. Used to select the timeout period for the watchdog timer.
WD1
0
0
1
1
Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register.
To power down the dc-to-dc converters, all channel outputs must first be disabled.
Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register.
D21
DUT_AD0
D12
0
CREG1 (D14)
0
0
1
1
0
WD0
0
1
0
1
D11
STATREAD
D20
1
D10
EWD
Timeout Period (ms)
5
10
100
200
D19
1
CREG0 (D13)
0
1
0
1
0
D9
WD1
D18
1
Rev. B | Page 29 of 44
D8
WD0
D17
DAC_AD1
D7
X
1
Main Control Register
The main control register options are shown in Table 17 and
Table 18. See the Device Features section for more information
on the features controlled by the main Control Register.
D16
DAC_AD0
D6
X
Main control register
Function
Slew rate control register (one per channel)
DAC control register (one per channel)
DC-to-dc control register
Software register
1
D5
OUTEN_ALL
D15
CREG2
D14
CREG1
D4
DCDC_ALL
CREG0
D13
D3 to D0
X
1
LSB
D12 to D0
Data
AD5757
LSB