AD5757 Analog Devices, AD5757 Datasheet - Page 39

• Manufacturer Part Number: AD5757
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5757

• Resolution (bits): 16bit
• Dac Update Rate: 60kSPS
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: SPI

Data Sheet
Using slew rate control can greatly reduce the AV
rent requirements, as shown in Figure 61. When using slew rate
control, attention should be paid to the fact that the output cannot
slew faster than the dc-to-dc converter. The dc-to-dc converter
slews slowest at higher currents through large (for example, 1
kΩ) loads. This slew rate is also dependent on the configuration
of the dc-to-dc converter. Two examples of the dc-to-dc converter’s
output slew are shown in Figure 59 and Figure 60 (V
sponds to the dc-to-dc converter’s output voltage).
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Figure 60. AI
Figure 59. AI
0
0
0
0
0mA TO 24mA RANGE
1kΩ LOAD
f
INDUCTOR = 10µH (XAL4040-103)
T
SW
A
= 25°C
= 410kHz
with External 51 kΩ Compensation Resistor
with External 51 kΩ Compensation Resistor
AI
I
V
CC
OUT
CC
0.5
0.5
BOOST
CC
Current vs. Time for 24 mA Step Through 500 Ω Load
Current vs. Time for 24 mA Step Through 1 kΩ Load
1.0
1.0
TIME (ms)
TIME (ms)
AI
I
V
INDUCTOR = 10µH (XAL4040-103)
OUT
BOOST
CC
1.5
1.5
0mA TO 24mA RANGE
AV
5.0V
CC
DAC A
SW
f
Figure 62. Configuration off a Particular Channel Using IGATE
SW
A
2.0
2.0
500Ω LOAD
SWGND
DAC CHANNE L A
T
(LEFT FLOATING)
= 410kHz
A
CC
= 25°C
supplies cur-
A
BOOST
2.5
2.5
32
28
24
20
16
12
8
4
0
32
28
24
20
16
12
8
4
0
corre-
R2
R1
Rev. B | Page 39 of 44
V
BOOST_A
(V
BOOST_A
EXTERNAL PMOS MODE
The AD5757 can also be used with an external PMOS transistor
per channel, as shown in Figure 62. This mode can be used to
limit the on-chip power dissipation of the AD5757, though this
will not reduce the power dissipation of the total system. The
IGATE functionality is not typically required when using the
dynamic power control feature so Figure 62 shows the configura-
tion of the device for a fixed V
In this configuration the SW
GNDSW
minimum supply of 7.5 V and a maximum supply of 33 V. This
supply can be sized according to the maximum load required to
be driven.
The IGATE functionality works by holding the gate of the
external PMOS transistor at (V
the majority of the channels power dissipation will take place in
this external PMOS transistor.
The external PMOS transistor should be chosen tolerate a V
voltage of at least −V
dissipation required. This external PMOS transistor typically
has minimal effect on the current output performance.
–5V)
R3
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Figure 61. AI
0
0
I
IGATEA
R
CHARTA
OUT_A
SET_A
x
pin is grounded. The V
0mA TO 24mA RANGE
1kΩ LOAD
f
INDUCTOR = 10µH (XAL4040-103)
T
SW
A
AI
I
V
= 25°C
OUT
BOOST
= 410kHz
1
CC
CC
CURRENT OUTPUT
R
Current vs. Time for 24 mA Step Through 1 kΩ Load
LOAD
BOOST_x
2
with Slew Rate Control
TIME (ms)
, as well as to handle the power
x
pin are left floating and the
3
BOOST_x
BOOST_x
BOOST_x
supply.
− 5 V). This means that
4
pin is connected to a
5
AD5757
6
32
28
24
20
16
12
8
4
0
DS