AD5757 Analog Devices, AD5757 Datasheet - Page 35

• Manufacturer Part Number: AD5757
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5757

• Resolution (bits): 16bit
• Dac Update Rate: 60kSPS
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: SPI

Data Sheet
If the error check fails, the FAULT pin goes low and the PEC
error bit in the status register is set. After reading the status
register, FAULT returns high (assuming there are no other
faults), and the PEC error bit is cleared automatically.
FAULT
The PEC can be used for both transmit and receive of data
packets. If status readback during a write is enabled, the PEC
values returned during the status readback during a write
operation should be ignored. If status readback during a write is
disabled, the user can still use the normal readback operation to
monitor status register activity with PEC.
WATCHDOG TIMER
When enabled, an on-chip watchdog timer generates an alert
signal if 0x195 has not been written to the software register
within the programmed timeout period. This feature is useful
to ensure that communication has not been lost between the
MCU and the AD5757 and that these datapath lines are working
properly (that is, SDIN, SCLK, and SYNC ). If 0x195 is not
received by the software register within the timeout period,
the ALERT pin signals a fault condition. The ALERT signal is
active high and can be connected directly to the CLEAR pin to
enable a CLEAR in the event that communication from the
MCU is lost.
The watchdog timer is enabled, and the timeout period (5 ms,
10 ms, 100 ms, or 200 ms) is set in the main control register (see
Table 17 and Table 18).
OUTPUT ALERT
The AD5757 is equipped with an ALERT pin. This is an active
high CMOS output. The AD5757 also has an internal watchdog
timer. When enabled, it monitors SPI communications. If 0x195
is not received by the software register within the timeout period,
the ALERT pin goes active.
SYNC
SYNC
SCLK
SCLK
SDIN
SDIN
MSB
D23
MSB
D31
32-BIT DATA TRANSFER WITH ERROR CHECKING
24-BIT DATA TRANSFER—NO ERROR CHECKING
UPDATE ON SYNC HIGH
24-BIT DATA
24-BIT DATA
Figure 54. PEC Timing
ONLY IF ERROR CHECK PASSED
LSB
LSB
UPDATE ON SYNC HIGH
D0
D8
IF ERROR CHECK FAILS
FAULT PIN GOES LOW
D7
8-BIT CRC
D0
Rev. B | Page 35 of 44
INTERNAL REFERENCE
The AD5757 contains an integrated 5 V voltage reference with
initial accuracy of ±5 mV maximum and a temperature drift
coefficient of ±10 ppm maximum. The reference voltage
is buffered and externally available for use elsewhere within
the system.
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 49, R
of the voltage to current conversion circuitry. The stability of
the output current value over temperature is dependent on the
stability of the value of R
stability of the output current over temperature, an external
15 kΩ low drift resistor can be connected to the R
the AD5757 to be used instead of the internal resistor, R1.
The external resistor is selected via the DAC control register
(see Table 19).
Table 1 outlines the performance specifications of the AD5757
with both the internal R
resistor. Using an external R
performance over the internal R
R
performance depends on the absolute value and temperature
coefficient of the resistor used. This directly affects the gain error
of the output, and thus the total unadjusted error. To arrive at
the gain/TUE error of the output with a particular external R
resistor, add the percentage absolute error of the R
directly to the gain/TUE error of the AD5757 with the external
R
HART
The AD5757 has four CHART pins, one corresponding to each
output channels. A HART signal can be coupled into these pins.
The HART signal appears on the corresponding current output,
if the output is enabled. Table 30 shows the recommended input
voltages for the HART signal at the CHART pin. If these
voltages are used, the current output should meet the HART
amplitude specifications. Figure 55 shows the recommended
circuit for attenuating and coupling in the HART signal.
Table 30. CHART Input Voltage to HART Output Current
R
Internal R
External R
A minimum capacitance of C1 + C2 is required to ensure that
the 1.2 kHz and 2.2 kHz HART frequencies are not significantly
attenuated at the output. The recommended values are C1 =
22 nF, C2 = 47 nF.
SET
SET
SET
resistor specification assumes an ideal resistor; the actual
resistor, shown in Table 1 (expressed in % FSR).
SET
SET
CHART Input
Voltage
150 mV p-p
170 mV p-p
HART MODEM
OUTPUT
Figure 55. Coupling HART Signal
SET
SET
SET
resistor and an external, 15 kΩ R
. As a method of improving the
is an internal sense resistor as part
SET
C1
resistor allows for improved
SET
resistor option. The external
C2
CHARTx
Current Output
(HART)
1 mA p-p
1 mA p-p
SET_x
SET
AD5757
resistor
pin of
SET
SET