AD5757 Analog Devices, AD5757 Datasheet - Page 33

• Manufacturer Part Number: AD5757
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5757

• Resolution (bits): 16bit
• Dac Update Rate: 60kSPS
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: SPI

Data Sheet
Status Register
The status register is a read only register. This register contains
any fault information as a well as a ramp active bit and a user
toggle bit. When the STATREAD bit in the main control
Table 28. Decoding the Status Register
MSB
D15
DC-
DCD
1
Table 29. Status Register Options
Bit
DC-DCD
DC-DCC
DC-DCB
DC-DCA
User toggle
PEC Error
Ramp Active
Over TEMP
I
I
I
I
OUT_D
OUT_C
OUT_B
OUT_A
X = don’t care.
Fault
Fault
Fault
Fault
D14
DC-
DCC
D13
DC-
DCB
D12
DC-
DCA
Description
User toggle bit. This bit is set or cleared via the software register. This can be used to verify data communications if
needed.
Denotes a PEC error on the last data-word received over the SPI interface.
This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel).
This bit is set if the AD5757 core temperature exceeds approximately 150°C.
This bit is set if a fault is detected on the I
This bit is set if a fault is detected on the I
This bit is set if a fault is detected on the I
This bit is set if a fault is detected on the I
This bit is set on Channel D if the dc-to-dc converter cannot maintain compliance (it may be reaching its V
voltage). In this case, the I
information on this bit’s operation under this condition.
This bit is set on Channel C if the dc-to-dc converter cannot maintain compliance (it may be reaching its V
voltage). In this case, the I
information on this bit’s operation under this condition.
This bit is set on Channel B if the dc-to-dc converter cannot maintain compliance (it may be reaching its V
voltage). In this case, the I
information on this bit’s operation under this condition.
This bit is set on Channel A if the dc-to-dc converter cannot maintain compliance (it may be reaching its V
voltage). In this case, the I
information on this bit’s operation under this condition.
D11
User
toggle
D10
PEC
error
OUT_D
OUT_C
OUT_B
OUT_A
D9
Ramp
active
fault bit is also set. See the DC-to-DC Converter V
fault bit is also set. See the DC-to-DC Converter V
fault bit is also set. See the DC-to-DC Converter V
fault bit is also set. See the DC-to-DC Converter V
D8
Over
TEMP
Rev. B | Page 33 of 44
OUT_D
OUT_C
OUT_B
OUT_A
D7
X
pin.
pin.
pin.
pin.
1
register is set, the status register contents can be read back on
the SDO pin during every write sequence. Alternatively, if the
STATREAD bit is not set, the status register can be read using
the normal readback operation.
D6
X
1
D5
X
1
D4
X
1
MAX
MAX
MAX
MAX
Functionality section for more
Functionality section for more
Functionality section for more
Functionality section for more
D3
I
fault
OUT_D
D2
I
fault
OUT_C
D1
I
fault
OUT_B
AD5757
MAX
MAX
MAX
MAX
LSB
D0
I
fault
OUT_A