ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 21

• Manufacturer Part Number: ADAU1445
• Manufacturer: Analog Devices

Specifications of ADAU1445

• Instructions/cycles: 3584
• Digital I/o Channels: 24/24
• Analog I/o Channels: 0/0
• Product Description: Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

MASTER CLOCK AND PLL
Using the Oscillator
The ADAU1442/ADAU1445/ADAU1446 can use an on-board
oscillator to generate its master clock. However, an external crystal
must be attached to complete the oscillator circuit. The on-board
oscillator is designed to work with a 256 × f
which is 12.288 MHz when f
when f
should be in this range even when the core is processing dual-
or quad-rate signals. When the core is processing dual-rate
signals (for example, f
frequency of the crystal should be 128 × f
is processing quad-rate signals (for example, f
the resonant frequency of the crystal should be 64 × f
The external crystal in the circuit should be an AT-cut parallel
resonance device operating at its fundamental frequency.
Ceramic resonators should not be used. Figure 9 shows the
crystal oscillator circuit recommended for proper operation.
The 100 Ω damping resistor on XTALO provides the oscillator
with a voltage swing of approximately 2.2 V at the XTALI pin.
The crystal shunt capacitance should be 7 pF. Its optimal load
capacitance, specified by the manufacturer, should be about 18 pF,
although the circuit supports values up to 25 pF. The equivalent
series resistance should also be as small as possible. The necessary
values of Load Capacitor C1 and Load Capacitor C2 can be
calculated from the crystal load capacitance with the following
equation:
where C
assumed to be approximately 2 pF to 5 pF.
Short trace lengths in the oscillator circuit decrease stray
capacitance, thereby increasing the loop gain of the circuit and
helping to avoid crystal start-up problems.
On the ADAU1442/ADAU1445/ADAU1446 evaluation boards,
the capacitance value for C1 and C2 is 22 pF.
XTALO should not be used to directly drive the crystal signal to
another IC. This signal is an analog sine wave and is not appro-
priate to drive a digital input. A separate pin, CLKOUT, is provided
C
S,NORMAL
L
STRAY
=
C
C
1
1
is the stray capacitance in the circuit and is usually
is 44.1 kHz. The resonant frequency of this crystal
×
+
C
C
2
2
Figure 9. Crystal Oscillator Circuit
+
C
S,DUAL
C1
C2
STRAY
= 88.2 kHz or 96 kHz), resonant
S,NORMAL
100Ω
is 48 kHz and 11.2896 MHz
XTALO
XTALI
S,DUAL
S,NORMAL
S,QUAD
. When the core
master clock,
= 192 kHz),
S,QUAD
.
Rev. C | Page 21 of 92
for this purpose. CLKOUT can output 256 × f
f
signal to other ICs in the system. CLKOUT is set up using the
CLKMODEx pins. For a more detailed explanation of CLKOUT,
refer to the Using the ADAU1442/ADAU1445/ADAU1446
as Clock Master section.
Setting Master Clock and PLL Mode
The ADAU1442/ADAU1445/ADAU1446 master clock input feeds
a PLL, which generates the 3584 × f
when f
to as f
must be one of the following: 64 × f
256 × f
is the audio sampling rate with the core in normal-rate processing
mode. The PLL divider mode is set by PLL0, PLL1, and PLL2 as
detailed in Table 9.
If the ADAU1442/ADAU1445/ADAU1446 cores are set to
receive dual-rate signals (by reducing the number of program
steps per sample by a factor of 2 using the DSP core rate select
register), then the master clock frequency must be 32 × f
64 × f
If the ADAU1442/ADAU1445/ADAU1446 cores are set to
receive quad-rate signals (by reducing the number of program
steps per sample by a factor of 4 using the DSP core rate select
register), then the master clock frequency must be 16 × f
32 × f
up, a clock signal must be present on XTALI so that the
ADAU1442/ADAU1445/ADAU1446 can complete its
initialization routine.
If at any point during operation the clock signal is removed
from XTALI, the DSP should be reset to avoid unpredictable
behavior on output pins. The clock mode should not be changed
without also resetting the ADAU1442/ADAU1445/ADAU1446.
If the mode is changed during operation, a click or pop can
result on the outputs. The state of the PLLx pins should be
changed while RESET is held low.
The phase-locked loop uses the PLL mode select pins (PLL0,
PLL1, and PLL2) to derive a 64 × f
signal is present at the XTALI pin. This clock signal is multiplied
by 56 to produce the core clock. Therefore, f
In a system with a f
clock and then multiplies it by 56 to produce a 172.032 MHz
core clock.
The core clock (f
though it may be lower in some applications.
S,NORMAL
S,DUAL
S,QUAD
CORE
S,NORMAL
S,NORMAL
, or a buffered, digital copy of the crystal oscillator
. In normal operation, the input to the master clock
, 128 × f
, 64 × f
ADAU1442/ADAU1445/ADAU1446
is 48 kHz) to run the DSP core. This rate is referred
, 384 × f
CORE
S,QUAD
S,NORMAL
S,DUAL
) should never exceed 172.032 MHz,
S,NORMAL
, 96 × f
, 192 × f
of 48 kHz, the PLL derives a 3.072 MHz
, or 512 × f
S,QUAD
S,DUAL
S,NORMAL
S,NORMAL
, or 128 × f
S,NORMAL
, or 256 × f
S,NORMAL
clock (172.032 MHz
CORE
clock from whatever
, 128 × f
S,QUAD
S,NORMAL
is 3584 × f
, where f
S,DUAL
S,NORMAL
. On power-
.
, 512 ×
S,DUAL
S,QUAD
S,NORMAL
S,NORMAL
,
,
,
.